Semiconductor device

A method, comprising:

• forming each of a first gate and a second gate on a first dielectric layer on a substrate of a semiconductor device;
• depositing a second dielectric layer on the first gate, the second gate, and the substrate;
• and
• forming one or more control gates entirely on one or more first portions of the second dielectric layer that reside on the substrate,
• wherein the one or more first portions of the second dielectric layer are different from one or more second portions of the second dielectric layer that reside on the first gate and the second gate,
• wherein, in a cross section of the semiconductor device, a top surface of the one or more second portions and a top surface of the one or more control gates are coplanar.

A method, comprising:

• forming a first floating gate on a first portion of a first dielectric layer on a substrate of a semiconductor device;
• forming a second floating gate on a second portion of the first dielectric layer;
• forming, after forming the first floating gate and the second floating gate, a first source or drain in a first portion of the substrate that is between the first floating gate and the second floating gate;
• depositing, after forming the first source or drain, a second dielectric layer directly on the first floating gate, the second floating gate, the first portion of the substrate, and one or more second portions of the substrate,
• wherein one or more second portions of the substrate are different from the first portion of the substrate and reside outside of the first floating gate and the second floating gate;
• and
• forming a first control gate entirely on a first portion of the second dielectric layer that resides on the first portion of the substrate or the one or more second portions of the substrate,
• wherein the first portion of the second dielectric layer is different from one or more second portions of the second dielectric layer that reside on the first floating gate and the second floating gate,
• wherein, in a cross section of the semiconductor device, a top surface of the one or more second portions and a top surface of the first control gate are coplanar.