Synchronization circuit and synchronization chip

A synchronization circuit, comprising M group synchronization signal generating circuits and a node synchronization signal generating circuit, M being a positive integer, wherein

• an input terminal of each group synchronization signal generating circuit in the M group synchronization signal generating circuits is configured to connect to N nodes, N being a positive integer, and N being greater than or equal to M;
• an output terminal of each group synchronization signal generating circuit in the M group synchronization signal generating circuits is connected to the node synchronization signal generating circuit;
• an output terminal of the node synchronization signal generating circuit is configured to connect to the N nodes;
• the group synchronization signal generating circuit is configured to generate a synchronization indication signal;
• and
• the node synchronization signal generating circuit is configured to generate a synchronization signal based on the synchronization indication signal generated by the group synchronization signal generating circuit,
• wherein each group synchronization signal generating circuit in the M group synchronization signal generating circuits comprises a node synchronization indicator, a synchronization ready signal generator, and a group node synchronization indication signal generator;
• the node synchronization indicator is configured to indicate to-be-synchronized nodes in the N nodes;
• the synchronization ready signal generator is configured to generate a synchronization ready signal when each node in the to-be-synchronized nodes is ready for synchronization;
• the group node synchronization indication signal generator is configured to generate the synchronization indication signal based on the synchronization ready signal;
• the group node synchronization indication signal generator is further configured to:
• generate, in response to receiving the synchronization ready signal, the synchronization indication signal corresponding to the to-be-synchronized nodes indicated by the node synchronization indicator;
• and
• the node synchronization indicator comprises a register, the register comprises at least N register bits, the N register bits are in one-to-one correspondence with the N nodes, register bits that correspond to the to-be-synchronized nodes in the N register bits are configured as a first value, and register bits that correspond to nodes other than the to-be-synchronized nodes in the N nodes in the N register bits are configured as a second value.