Multiplexed higher order sigma-delta analog-to-digital converter

A sigma-delta analog-to-digital conversion method for digitizing analog input signals of at least two input channels by a multiplexed sigma-delta analog-to-digital converter (ADC), the method comprising:

• integrating a sample of one of said at least two input channels at a time by a multiplexed integrator chain, the integrating including:
• integrating the sample by a first delaying integrator in the integrator chain, wherein operation of the first delaying integrator is controlled by a first clock set comprising first clocks and first channel selection clocks,
• integrating the sample by a first non-delaying integrator disposed in the integrator chain right after the first delaying integrator, wherein the first non-delaying integrator is controlled by the first clock set, and
• integrating the sample by a second delaying integrator disposed in the integrator chain topologically after the first delaying integrator, wherein the second delaying integrator is controlled by a second clock set comprising second clocks and second channel selection clocks;
• quantizing an output of a last integrator in the integrator chain to provide an output of the multiplexed sigma-delta ADC;
• delaying the second channel selection clock set relative to the first channel selection clock set to prevent data from being mixed between consecutive full clock cycles;
• feeding back a first feedback signal at an input of the first delaying integrator;
• and
• feeding back a second feedback signal at respective inputs of the first non-delaying integrator and the second delaying integrator,
• wherein the first and second feedback signals represent an analog value that corresponds to a digital signal at an output of the multiplexed sigma-delta ADC.

A sigma-delta analog-to-digital conversion method for digitizing analog input signals of at least two input channels by a multiplexed sigma-delta analog-to-digital converter (ADC), the method comprising:

• integrating a sample of one of said at least two input channels at a time by a multiplexed integrator chain, the integrating including:
• integrating the sample by a first delaying integrator in the integrator chain, wherein operation of the first delaying integrator is controlled by a first clock set comprising first clocks and first channel selection clocks,
• integrating the sample by a first non-delaying integrator disposed in the integrator chain right after a second delaying integrator, wherein the first non-delaying integrator is controlled by a second clock set comprising second clocks and second channel selection clocks, and
• integrating the sample by the second delaying integrator disposed in the integrator chain topologically after the first non-delaying integrator, wherein the second delaying integrator is controlled by the second clock set;
• quantizing an output of a last integrator in the integrator chain to provide an output of the multiplexed sigma-delta ADC;
• delaying the second channel selection clock set relative to the first channel selection clock set to prevent data from being mixed between consecutive full clock cycles;
• feeding back a first feedback signal at an input of the first delaying integrator;
• and
• feeding back a second feedback signal at respective inputs of the first non-delaying integrator and the second delaying integrator,
• wherein the first and second feedback signals represent an analog value that corresponds to a digital signal at an output of the multiplexed sigma-delta ADC.