Synchronizing digital device

A system, comprising:

• a master device;
• a bus system coupled to the master device, wherein the bus system has a bus clock signal having a bus clock frequency;
• and
• a slave device coupled to the bus system, the slave device including:
• a local oscillator, which, in operation, generates a local clock signal having a local clock frequency;
• an all-digital phase locked loop (ADPLL) coupled to the local oscillator, wherein ADPLL, in operation, generates a sampling control signal, the ADPLL including:
• a phase-error detector, which, in operation, generates a phase error signal based on a loop clock signal and the bus clock signal;
• a digital filter coupled to the phase-error detector, wherein the digital filter, in operation, generates a signal indicative of a frequency ratio between a frequency of the bus clock signal and the local clock frequency based on the phase error signal;
• and
• a sigma-delta modulator coupled to the digital filter, wherein the sigma-delta modulator, in operation, generates a modulated signal based on the signal indicative of the frequency ratio generated by the digital filter, and the sampling control signal is based on the modulated signal;
• digital signal generating circuitry coupled to the local oscillator, wherein the digital signal generating circuitry, in operation, generates digital signals;
• sampling circuitry, coupled to the digital signal generating circuitry and to the ADPLL, wherein the sampling circuitry, in operation, samples digital signals generated by the digital signal generating circuitry at a sampling frequency which is a function of the sampling control signal;
• and
• an interface coupled to the sampling circuitry and to the bus system, wherein the interface, in operation, outputs sampled data signals.

A method, comprising:

• generating, using a local oscillator of a slave device, a local clock signal having a local clock frequency;
• generating digital signals using the local clock signal;
• generating, using an all-digital phase locked loop (ADPLL) coupled to the local oscillator, a sampling control signal;
• sampling the generated digital signals at a sampling frequency which is a function of the sampling control signal;
• and
• generating an output of the slave device based on the sampled digital signals, wherein the generating the sampling control signal comprises:
• generating a phase error signal based on a loop clock signal and a reference clock signal;
• generating a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal;
• and
• generating, using a sigma-delta modulator, a modulated signal based on the signal indicative of the frequency ratio;
• and
• generating the sampling control signal based on the modulated signal.