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AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsBenjamin Thomas Sander, Swapnil Sakharshete, Ashish Panday
Estimating the term…
Systems, apparatuses, and methods for achieving higher cache hit rates for machine learning models are disclosed. When a processor executes a given layer of a machine learning model, the processor generates and stores activation data in a cache subsystem a forward or reverse manner. Typically, the entirety of the activation data does not fit in the cache subsystem. The processor records the order in which activation data is generated for the given layer. Next, when the processor initiates execution of a subsequent layer of the machine learning model, the processor processes the previous layer's activation data in a reverse order from how the activation data was generated. In this way, the processor alternates how the layers of the machine learning model process data by either starting from the front end or starting from the back end of the array.
A processor comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.