Signal reflection mitigation systems
AssigneeHamilton Sundstrand Corporation
InventorDale Blankenship
Life of this patent
Estimating the term…
Abstract
A circuit can include a closed loop bus line having a plurality of connections. The circuit can include a plurality of integrated circuits disposed on the close loop bus line at a respective connection of the plurality of connections. One or more of the integrated circuits can be configured to drive a signal on the closed loop bus line. The closed loop bus line can be configured to prevent signal reflection. For example, in certain embodiments, there are no termination resistors at any of the terminations to reduce size, weight, and/or part count of the circuit.
Claims22
A circuit, comprising:
- a printed circuit board (PCB) that includes:
- a closed loop data bus line having a first plurality of connections;
- a closed loop address bus line having a second plurality of connections;
- and
- a plurality of integrated circuits (ICs) each disposed on the closed loop data bus line at a respective connection of the first plurality of connections and on the closed loop address bus line at a respective connection of the second plurality of connections, wherein the plurality of ICs includes (i) a plurality of static random-access memory (SRAM) components configured to drive signals on the closed loop data bus line and the closed loop address bus line and (ii) a field programmable gate array (FPGA), wherein the closed loop data bus line and the closed loop address bus line are configured to prevent signal reflection, and wherein there are no termination resistors at any terminations to reduce size, weight, and/or part count of the circuit.
An aircraft system, comprising:
- a circuit having a printed circuit board (PCB) that includes:
- a closed loop data bus line having a first plurality of connections;
- a closed loop address bus line having a second plurality of connections;
- and
- a plurality of integrated circuits (ICs) each disposed on the closed loop data bus line at a respective connection of the first plurality of connections and on the closed loop address bus line at a respective connection of the second plurality of connections, wherein the plurality of ICs includes (i) a plurality of static random-access memory (SRAM) components configured to drive signals on the closed loop data bus line and the closed loop address bus line and (ii) a field programmable gate array (FPGA), wherein the closed loop data bus line and the closed loop address bus line are configured to prevent signal reflection, and wherein there are no termination resistors at any terminations to reduce size, weight, and/or part count of the circuit.
A method, comprising:
- defining, on a printed circuit board (PCB), a closed loop data bus line and a closed loop address bus line for a plurality of integrated circuits (ICs) to connect to;
- and
- directly connecting the plurality of ICs to the closed loop data bus line and the closed loop address bus line without any termination resistors, wherein the plurality of ICs includes (i) a plurality of static random-access memory (SRAM) components configured to drive signals on the closed loop data bus line and the closed loop address bus line and (ii) a field programmable gate array (FPGA).
Dependencies are inferred from the claim text.