Test time reduction in circuits with redundancy flip-flops
AssigneeSTMicroelectronics International N.V.
InventorsSandeep Jain, Akshay Kumar Jain, Jeena Mary George
Life of this patent
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Abstract
According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.
Claims20
A digital circuit, comprising:
- N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the digital circuit configured to operate in a functional mode corresponding to a regular operation of the digital circuit and a test mode corresponding to testing of various paths of the digital circuit,
- wherein the digital circuit, during the functional mode, is configured to:
- combine a functional output signal of each of the N number of redundant flip-flops using logic gates;
- and
- provide a single functional output signal in a fault-tolerant, safety-critical system based on the combining, and
- wherein the digital circuit, during the test mode, is configured to:
- arrange a first flip-flop of the N number of redundant flip-flops as part of a test path;
- arrange N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal;
- observe a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop;
- and
- observe test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are observed at a same test cycle.
An integrated circuit comprising a digital circuit, the digital circuit comprising:
- N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the digital circuit configured to operate in a functional mode corresponding to a regular operation of the digital circuit and a test mode corresponding to testing of various paths of the digital circuit,
- wherein the digital circuit, during the functional mode, is configured to:
- combine a functional output signal of each of the N number of redundant flip-flops using logic gates;
- and
- provide a single functional output signal in a fault-tolerant, safety-critical system based on the combining, and
- wherein the digital circuit, during the test mode, is configured to:
- arrange a first flip-flop of the N number of redundant flip-flops as part of a test path;
- arrange N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal;
- observe a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop;
- and
- observe test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are observed at a same test cycle.
A method of operating a digital circuit having N number of redundant flip-flops, each of the N number of redundant flip-flops having a data input coupled to a common data signal, the method comprising:
- operating the digital circuit in a functional mode corresponding to a regular operation of the digital circuit, wherein, during the functional mode, the method comprises:
- combining a functional output signal of each of the N number of redundant flip-flops using logic gates;
- and
- providing a single functional output signal in a fault-tolerant, safety-critical system based on the combining;
- and
- operating the digital circuit in a test mode corresponding to testing of various paths of the digital circuit, wherein, during the test mode, the method comprises:
- arranging a first flip-flop of the N number of redundant flip-flops as part of a test path,
- arranging N−1 number of the N number of redundant flip-flops as shadow logic by bypassing the N−1 number of the N number of redundant flip-flops from the test path, the N number of redundant flip-flops receiving a test pattern at the common data signal,
- observing a test output signal at an output terminal of the first flip-flop to determine faults within a test path comprising the first flip-flop, and
- observing test output signals of each of the N−1 number of redundant flip-flops to determine faults within the N−1 number of redundant flip-flops, wherein observing the test output signal at the output terminal of the first flip-flop and the test output signals of each of the N−1 number of redundant flip-flops are during a same test cycle.
Dependencies are inferred from the claim text.