Memory profiler for emulation

An emulation system comprising:

• a processor;
• a field programmable gate array (FPGA);
• a user memory comprising a plurality of ports and connected to the FPGA;
• and
• a profiler memory comprising a plurality of ports and coupled to the user memory, an address port from among the plurality of ports of the profiler memory being connected to an address port of the plurality of ports of the user memory, wherein the profiler memory is configured to:
• track most significant bits (MSB) of one or more addresses of the user memory accessed by the FPGA in response to a first test sequence of a testbench during an emulation;
• and
• determine page indexes of one or more pages of the user memory associated with the one or more addresses of the user memory accessed by the FPGA in response to the first test sequence, and
• wherein the processor is configured to determine a sparse memory size for the user memory based on the page indexes of the one or more pages of the user memory associated with the one or more addresses of the user memory accessed by the FPGA in response to one or more test sequences of the testbench,
• wherein the user memory is divided into a plurality of pages, and
• wherein each page in the user memory is mapped to a corresponding address in the profiler memory.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• instantiate a profiler memory having a plurality of ports connected to corresponding ports of a user memory, the profiler memory being configured to:
• determine that one or more pages of the user memory are accessed by a first test sequence of a testbench for an emulation;
• track most significant bits (MSB) of one or more addresses of the user memory used in the first test sequence of the testbench for the emulation;
• determine page indexes of the one or more pages of the user memory associated with the one or more addresses of the user memory used in the first test sequence;
• identify a first set of indexes of the one or more pages of the user memory used by the first test sequence;
• store the first set of indexes in a storage device;
• determine a number of unique pages of the user memory that are used by the first test sequence for the emulation;
• and
• determine a size of a sparse memory for the user memory based on the number of unique pages of the user memory that are used by the testbench for the emulation and a page size of the user memory,
• wherein the user memory is divided into a plurality of pages, and
• wherein each page in the user memory is mapped to a corresponding address in the profiler memory.