Coding circuit and memory device including the same
AssigneesSK hynix Inc., Korea University Research and Business Foundation
InventorsMinseo Kim, Jongsun Park, Jinho Jeong
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Abstract
A coding circuit includes an encoder circuit configured to generate an input codeword by concatenating an input data and a parity generated by processing the input data using an odd parity generator matrix; and a decoder circuit configured to correct a double error from an output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix, wherein each column of the odd parity generator matrix has a respective odd number of 1's.
Claims12
A coding circuit comprising:
- an encoder circuit configured to generate an input codeword by concatenating an input data and a parity generated by processing the input data using an odd parity generator matrix;
- and
- a decoder circuit configured to correct a double error from an output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix,
- wherein each column of the odd parity generator matrix has a respective odd number of 1's, and
- wherein the odd parity generator matrix corresponds to a plurality of selected columns selected from a generator matrix corresponding to a predetermined generator function for Bose-Chauduri-Hocquenghem (BCH) coding on a finite field GF (2m), each selected column having a respective odd number of 1's.
A memory device comprising:
- a memory cell array;
- and
- a coding circuit configured to provide an input codeword to the memory cell array by encoding input data, and to generate output data and a detection signal by decoding an output codeword output from the memory cell array,
- wherein the coding circuit includes:
- an encoder circuit configured to generate the input codeword by concatenating the input data and a parity generated by processing the input data using an odd parity generator matrix;
- and
- a decoder circuit configured to correct a double error from the output codeword, and to detect a triple error using a syndrome generated by processing the output codeword using the odd parity generator matrix,
- wherein each column of the odd parity generator matrix has a respective odd number of 1's, and
- wherein the odd parity generator matrix corresponds to a plurality of columns selected from a generator matrix corresponding to a predetermined generator function for Bose-Chauduri-Hocquenghem (BCH) coding on a finite field GF (2m), each selected column having a respective odd number of 1's.
Dependencies are inferred from the claim text.