Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter

Circuitry for digital-to-analog conversion, comprising:

• a driver circuit:
• a weighting resistor circuit coupled to an output of the driver circuit, the weighting resistor circuit comprising:
• a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node;
• a second resistive sub-circuit coupled to the intermediate node and a common node;
• and
• a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry, wherein the resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit,
• wherein the first resistive sub-circuit comprises:
• a first additional resistive sub-circuit coupled between the output of the driver circuit and an additional intermediate node;
• a second additional resistive sub-circuit coupled between the additional intermediate node and the common node;
• and
• a third additional resistive sub-circuit coupled between the additional intermediate node and the intermediate node, wherein the resistivity of the second additional resistive sub-circuit is equal to or smaller than the resistivity of the first additional resistive sub-circuit.

Circuitry for digital-to-analog conversion, comprising:

• a driver circuit;
• a weighting resistor circuit coupled to an output of the driver circuit, the weighting resistor circuit comprising:
• a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node;
• a second resistive sub-circuit coupled to the intermediate node and a common node;
• and
• a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry, wherein the resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit,
• wherein the third resistive sub-circuit comprises:
• a first additional resistive sub-circuit coupled between the intermediate node and an additional intermediate node;
• a second additional resistive sub-circuit coupled between the additional intermediate node and the common node;
• and
• a third additional resistive sub-circuit coupled between the additional intermediate node and the output of the circuitry, wherein the resistivity of the second additional resistive sub-circuit is equal to or smaller than the resistivity of the first additional resistive sub-circuit.