Successive approximation register (SAR) analog- to-digital converter (ADC) with input-dependent least significant bit (LSB) size
AssigneeQUALCOMM Incorporated
InventorBehnam Sedighi
Life of this patent
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Abstract
Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.
Claims27
A successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal, wherein the SAR ADC is configured to output N bits, and wherein the SAR ADC is configured to convert the analog input signal to the digital output signal using less than N comparisons.
A successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
- a capacitive digital-to-analog converter (CDAC) comprising an array of switched capacitors;
- a comparator having an input coupled to an output of the CDAC;
- and
- logic having an input coupled to an output of the comparator, wherein:
- two or more most significant bit (MSB) capacitors in the array of switched capacitors have non-binary weighting;
- the logic has a first output with N bits for a digital output signal;
- the logic has a second output with two or more bits for controlling the two or more MSB capacitors based on one or more MSBs of the digital output signal;
- and
- remaining capacitors in the array of switched capacitors are configured to be controlled by at least a portion of remaining bits of the digital output signal.
A method of signal conversion, the method comprising converting an analog input signal to a digital output signal using a successive approximation register (SAR) analog-to-digital converter (ADC), wherein a quantization size of a least significant bit (LSB) associated with the digital output signal depends on an amplitude of the analog input signal, wherein the SAR ADC is configured to output N bits, and wherein the converting comprises making less than N comparisons to generate the N bits.
Dependencies are inferred from the claim text.