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US 12,261,577 B2Granted
Amplifier peak detection
AssigneeQUALCOMM Incorporated
InventorsJeremy Goldblatt, Arul Balasubramaniyan, Chinmaya Mishra, Damin Cao, Bhushan Shanti Asuri
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Abstract
A peak detector for a power amplifier is provided that includes a threshold voltage detector configured to pulse a detection current in response to an amplified output signal from the amplifier exceeding a peak threshold. A plurality of such peak detectors may be integrated with a corresponding plurality of power amplifiers in a transmitter. Should any peak detector assert an alarm signal or more than a threshold number of alarm signals during a given period, a controller reduces a gain for the plurality of power amplifiers.
Claims24
A peak detector, comprising:
- a voltage divider configured to divide an amplifier output signal into a divided signal;
- a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
- a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node;
- and
- at least one inverter configured to invert a voltage of the node to produce a binary output signal,
- wherein the threshold voltage detector comprises
- a first transistor having a gate configured to be driven by the divided signal,
- a source bias circuit configured to bias a source of the first transistor,
- a gate bias circuit configured to bias a gate of the first transistor, and
- a drain bias circuit configured to bias a drain of the first transistor,
- wherein the source bias circuit comprises:
- a first current source configured to drive a resistor with a first current to develop a source bias voltage at a terminal of the resistor,
- a second transistor;
- a second current source configured to drive a second current into a drain of the second transistor;
- and
- a differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the source of the first transistor;
- and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the source of the first transistor with the source bias voltage.
14 more elements
A peak detector, comprising:
- a voltage divider configured to divide an amplifier output signal into a divided signal;
- a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
- a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node;
- and
- at least one inverter configured to invert a voltage of the node to produce a binary output signal,
- wherein the threshold voltage detector comprises
- a first transistor having a gate configured to be driven by the divided signal,
- a source bias circuit configured to bias a source of the first transistor,
- a gate bias circuit configured to bias a gate of the first transistor, and
- a drain bias circuit configured to bias a drain of the first transistor,
- wherein the gate bias circuit comprises:
- a first current source configured to drive a first resistor with a first current to develop a bias voltage at a terminal of the first resistor;
- a second transistor;
- a second current source configured to drive a second current into a drain of the second transistor;
- and
- a differential amplifier having a first input coupled to the terminal of the first resistor, a second input coupled to the drain of the second transistor;
- and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the gate of the first transistor with a gate bias voltage equal to the bias voltage at the terminal of the first resistor.
14 more elements
A peak detector, comprising:
- a voltage divider configured to divide an amplifier output signal into a divided signal;
- a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;
- a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node;
- and
- at least one inverter configured to invert a voltage of the node to produce a binary output signal,
- wherein the threshold voltage detector comprises
- a first transistor having a gate configured to be driven by the divided signal,
- a source bias circuit configured to bias a source of the first transistor,
- a gate bias circuit configured to bias a gate of the first transistor, and
- a drain bias circuit configured to bias a drain of the first transistor,
- wherein the drain bias circuit comprises:
- a first current source configured to drive a resistor with a first current to develop a drain bias voltage at a terminal of the resistor,
- a second transistor having a source coupled to a drain of the first transistor;
- a second current source configured to drive a second current into ground from the source of the second transistor;
- and
- a differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the drain of the first transistor;
- and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the drain of the first transistor with the drain bias voltage.
14 more elements
Dependencies are inferred from the claim text.