Spike current suppression in a memory array

An apparatus, comprising:

• an access line having a first portion and a second portion, wherein a gap physically separates the first portion and the second portion, wherein each of the first and second portions is configured to access respective memory cells on opposite sides of the gap, and wherein the memory cells are configured in a memory array;
• and
• a via electrically connected to the first and second portions, the via configured for coupling a voltage used to bias the first and second portions when accessing the memory cells.

An apparatus, comprising:

• an access line configured in a memory array, the access line having a first portion and a second portion, wherein the first portion is physically separate from the second portion, and each of the first and second portions is configured to access memory cells of the memory array;
• and
• a via electrically connected to the first and second portions, the via configured for coupling a voltage to the first and second portions when accessing the memory cells.