Multiply accumulate circuit for binary neural network system

A multiply accumulate circuit for a neural network system comprising m sub-multiply accumulate circuits, and a first sub-multiply accumulate circuit of the m sub the multiply accumulate circuits comprising:

• n non-volatile memory cells;
• and
• n current sources,
• wherein the first sub-multiply accumulate circuit receives n one-bit neuron values from a first layer of the neural network system;
• wherein n current paths are defined by the n non-volatile memory cells and the n current sources collaboratively, and the n current paths are connected between a first supply voltage and an output terminal of the first sub-multiply accumulate circuit,
• wherein a first current path of the n current paths is defined by a first non-volatile memory cell of the n non-volatile memory cells and a first current source of the n current sources, the first non-volatile memory cell of the n non-volatile memory cells and the first current source of the n current sources are connected in series between the first supply voltage and the output terminal of the first sub-multiply accumulate circuit, and a control terminal of the first current source receives a first one-bit neuron value of the n one-bit neuron values from the first layer,
• wherein the first current source of the n current sources is capable of providing a first current, a x′th current source of the n current sources is capable of providing a xth current, a magnitude of the xth current is equal to 2(x−1) times of a magnitude of the first current, m and n and x are integers, x is greater than 1, and x is less than or equal to n,
• wherein when the first non-volatile memory cell is in a first storage state corresponding to a high resistance value, a one-bit neuron connection weight stored in the first non-volatile memory cell has a first logic value, wherein when the first non-volatile memory cell is in a second storage state corresponding to a low resistance value, the one-bit neuron connection weight stored in the first non-volatile memory cell has a second logic value, and wherein the high resistance value is at least 1000 times the low resistance value.