Method and system for fabricating a MEMS device
AssigneeInvenSense, Inc.
InventorsDaesung Lee, Alan Cuthbertson
Life of this patent
Estimating the term…
Abstract
A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.
Claims23
A method comprising:
- depositing a first intermetal dielectric (IMD) layer over a substrate;
- depositing a first polysilicon layer over the first IMD layer;
- depositing a second IMD layer over the first polysilicon layer;
- etching a first portion of the second IMD layer to form a bumpstop region;
- etching a second portion of the second IMD layer to expose a first portion of the first polysilicon layer;
- subsequent to forming the bumpstop region and subsequent to exposing the first portion of the first polysilicon layer, depositing a second polysilicon layer over the second IMD layer and further over the first portion of the first polysilicon layer, wherein the second polysilicon layer directly connects to the first portion of the first polysilicon layer;
- etching a portion of the second polysilicon layer to form a patterned second polysilicon layer and to expose a portion of the second IMD layer, wherein the etching the portion of the second polysilicon layer forms the bumpstop and a plurality of electrodes;
- depositing a third IMD layer over the patterned second polysilicon layer and the exposed portion of the second IMD layer;
- forming a via through the third IMD layer to expose a first portion of the patterned second polysilicon layer;
- filling the via;
- forming a bond layer over the via;
- and
- etching a portion of the third IMD layer to expose a second portion of the patterned second polysilicon layer, wherein the second portion of the patterned second polysilicon layer is different from the first portion of the patterned second polysilicon layer.
A method comprising:
- forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate;
- depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer;
- forming a standoff over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed;
- and
- depositing a bond layer over the standoff.
A method comprising:
- depositing a first intermetal dielectric (IMD) layer over a substrate;
- depositing a first polysilicon layer over the first IMD layer;
- depositing a second IMD layer over the first polysilicon layer;
- etching the second IMD layer to form a standoff and a bumpstop;
- etching at least a portion of the second IMD layer other than the standoff and the bumpstop to form a via to expose a portion of the first polysilicon layer;
- depositing a second polysilicon layer over the standoff, the bumpstop, the exposed portion of the first polysilicon layer that connects the two polysilicon layers together, and the second IMD layer;
- depositing a bond layer over the second polysilicon layer;
- patterning the bond layer to cover the standoff;
- and
- patterning a portion of the second polysilicon layer to expose a portion of the second IMD layer and to form a plurality of electrodes.
Dependencies are inferred from the claim text.