Semiconductor integrated circuit, receiver device, and reception method

A semiconductor integrated circuit comprising:

• a first converter configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal;
• a second converter configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal;
• and
• an adjustment circuit configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value, wherein
• the adjustment circuit includes:
• a first circuit configured to update a first code based on the first digital value and the second digital value, and update a second code based on the first code;
• and
• a second circuit configured to calibrate a gain of the first digital value based on the first code, and calibrate a gain of the second digital value based on the second code,
• or
• a third circuit configured to update a third code based on the first digital value and the second digital value, and update a fourth code based on the third code;
• and
• a fourth circuit configured to calibrate a phase of the first clock signal based on the third code, and calibrate a phase of the second clock signal based on the fourth code.