Methods and devices for digital clock multiplication of a clock to generate a high frequency output
AssigneeIntel Corporation
InventorsAli Azam, Ashoke Ravi, Benjamin Jann
Life of this patent
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Abstract
A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.
Claims20
A digital clock multiplier (DCM) circuit comprising:
- a plurality of phase shift generators, each configured to:
- receive a respective driving clock phase of a plurality of driving clock phases;
- and
- generate a plurality of phase shifts based on the respective driving clock phase, wherein in the plurality of phase shift generators are delay lock loops (DLLs) or digitally controlled edge-interpolators (DCEIs);
- a plurality of power amplifier (PA) rows, wherein each of the plurality of phase shift generators is coupled to a respective one of the plurality of PA rows,
- wherein each PA row comprises a plurality of cascade switched capacitor power amplifier (SCPA) unit cells arranged into groups, each group of cascade SCPA unit cells configured to:
- receive one phase shift of the plurality of phase shifts based on the respective driving clock phase;
- and
- one or more processors configured to:
- disable one or more cascade SCPA unit cells of each group based on the plurality of phase shifts;
- generate an output signal for each group of the plurality of cascade SCPA unit cells;
- and
- combine the output signal of each group of the plurality of cascade SCPA unit cells to generate a PA row output signal.
A method comprising:
- receiving, by each of a plurality of phase shift generators, a respective driving clock phase of a plurality of driving clock phases;
- generating, by each of the plurality of phase shift generators, a plurality of phase shifts based on the respective driving clock phase, wherein in the plurality of phase shift generators are delay lock loops (DLLs) or digitally controlled edge-interpolators (DCEIs);
- receiving, by each group of cascade switched capacitor power amplifier (SCPA) unit cells of a power amplifier (PA) row, one phase shift of the plurality of phase shifts based on the respective driving clock phase;
- disabling, by each group of cascade SCPA unit cells, one or more cascade SCPA unit cells based on the plurality of phase shifts;
- generating an output signal for each group of cascade SCPA unit cells;
- and
- combining the output signal of each group of cascade SCPA unit cells to generate a PA row output signal.
Dependencies are inferred from the claim text.