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US 12,255,598 B2Granted
Interleaved CIC filter
AssigneeInvenSense, Inc.
InventorStefano Cappello
Life of this patent
Estimating the term…
Abstract
An interleaved cascaded integrator-comb (“CIC”) filter receives an interleaved sensor output signal, including a plurality of digitized sensor signals at an input clock rate. An integrator of the interleaved CIC filter processes the interleaved signal to output an integrated interleaved signal. A downsampler of the interleaved CIC filter buffers portions of the integrated interleaved corresponding to a decimation rate for the interleaved signal. The portions of the signals are provided to a comb filter, which outputs a decimated interleaved signal.
Claims19
A device for processing interleaved signals, comprising:
- an integrator configured to receive an interleaved signal and output an integrated interleaved signal, wherein the interleaved signal comprises a plurality of digital signals interleaved at an input clock rate;
- a downsampler coupled to the integrator to receive the integrated interleaved signal and buffer a portion of each of the digital signals of the integrated interleaved signal;
- and
- a comb filter coupled to the downsampler to receive the portions of the digital signal and to output a decimated interleaved signal corresponding to the portions of the digital signals interleaved at clock rate corresponding the input clock rate divided by a decimation rate, wherein the downsampler comprises a first-in first-out (FIFO) buffer, and wherein a number of storage elements of the FIFO buffer corresponds to the number of the plurality of digital signals, and wherein the portions of each of the digital signals are based on the decimation rate.
1 more element
A method for processing interleaved signals, comprising:
- receiving, at an integrator, an interleaved signal comprising a plurality of digital signals interleaved at an input clock rate;
- integrating, by the integrator, the interleaved signal to generate an integrated interleaved signal;
- receiving, at a downsampler, the integrated interleaved signal;
- buffering, by the downsampler, a portion of each of the digital signals of the integrated interleaved signal;
- interleaving, at the downsampler, the portions of the digital signal at a decimated clock rate corresponding the input clock rate divided by a decimation rate, wherein the downsampler comprises a ramp, and wherein a number of storage elements of the ramp corresponds to the number of the plurality of digital signals, and wherein the portions of each of the digital signals are based on the decimation rate;
- receiving, at a comb filter, the interleaved portions of the digital signals;
- filtering, by the comb filter, the interleaved portions of the digital signals;
- and
- outputting, from the comb filter, a decimated interleaved signal based on the filtered interleaved portions of the digital signals.
6 more elements
A device for processing interleaved signals, comprising:
- an integrator configured to receive an interleaved signal and output an integrated interleaved signal, wherein the interleaved signal comprises a plurality of digital signals interleaved at an input clock rate;
- a downsampler coupled to the integrator to receive the integrated interleaved signal and buffer a portion of each of the digital signals of the integrated interleaved signal;
- and
- a comb filter coupled to the downsampler to receive the portions of the digital signal and to output a decimated interleaved signal corresponding to the portions of the digital signals interleaved at clock rate corresponding the input clock rate divided by a decimation rate, wherein the downsampler comprises a ramp, and wherein a number of storage elements of the ramp corresponds to the number of the plurality of digital signals, and wherein the portions of each of the digital signals are based on the decimation rate.
1 more element
A method for processing interleaved signals, comprising:
- receiving, at an integrator, an interleaved signal comprising a plurality of digital signals interleaved at an input clock rate;
- integrating, by the integrator, the interleaved signal to generate an integrated interleaved signal;
- receiving, at a downsampler, the integrated interleaved signal;
- buffering, by the downsampler, a portion of each of the digital signals of the integrated interleaved signal;
- interleaving, at the downsampler, the portions of the digital signal at a decimated clock rate corresponding the input clock rate divided by a decimation rate, wherein the downsampler comprises a first-in first-out (FIFO) buffer, and wherein a number of storage elements of the FIFO buffer corresponds to the number of the plurality of digital signals, and wherein the portions of each of the digital signals are based on the decimation rate;
- receiving, at a comb filter, the interleaved portions of the digital signals;
- filtering, by the comb filter, the interleaved portions of the digital signals;
- and
- outputting, from the comb filter, a decimated interleaved signal based on the filtered interleaved portions of the digital signals.
6 more elements
Dependencies are inferred from the claim text.