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US 12,254,945 B2Granted
Neuromorphic device
AssigneeSamsung Electronics Co., Ltd.
InventorYoungnam Hwang
Life of this patent
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Abstract
A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.
Claims20
A neuromorphic device comprising:
- a first memory cell array comprising:
- first resistive memory cells connected to word lines, bit lines, and source lines,
- second resistive memory cells connected to the word lines, at least one redundancy bit line, and at least one redundancy source line, and
- third resistive memory cells connected to at least one redundancy word line, the bit lines, and the source lines,
- wherein the first memory cell array is configured to store weight data corresponding to a weight of a neural network in the first resistive memory cells, and generate a plurality of read currents based on input signals and the weight data;
- a second memory cell array comprising:
- first reference resistive memory cells connected to reference word lines, reference bit lines, and reference source lines,
- second reference resistive memory cells connected to the reference word lines, at least one redundancy reference bit line, and at least one redundancy reference source line,
- third reference resistive memory cells connected to at least one redundancy reference word line, the reference bit lines, and the reference source lines,
- wherein the second memory cell array is configured to generate a plurality of reference currents;
- and
- an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals based on the plurality of reference currents.
9 more elements
A neuromorphic device comprising:
- an input buffer configured to store input values of a neural network model;
- a plurality of sub-arrays configured to perform a multiply and accumulate (MAC) operation based on weights of the neural network model;
- a plurality of redundancy sub-arrays;
- a layer buffer storing information about at least one sub-array of the plurality of sub-arrays in which a fault has occurred;
- and
- a control unit configured to control the at least one sub-array in which the fault has occurred to be replaced with a first redundancy sub-array of the plurality of redundancy sub-arrays,
- wherein each of the plurality of sub-arrays comprises:
- a first memory cell array comprising:
- first resistive memory cells connected to word lines, bit lines, and source lines,
- second resistive memory cells connected to the word lines, at least one redundancy bit line, and at least one redundancy source line, and
- third resistive memory cells connected to at least one redundancy word line, the bit lines, and the source lines,
- wherein the first memory cell array is configured to store weight data corresponding to a weight of a neural network in the first resistive memory cells, and generate a plurality of read currents based on input signals and the weight data;
- a second memory cell array comprising:
- first reference resistive memory cells connected to reference word lines, reference bit lines, and reference source lines,
- second reference resistive memory cells connected to the reference word lines, at least one redundancy reference bit line, and at least one redundancy reference source line, and
- third reference resistive memory cells connected to at least one redundancy reference word line, the reference bit lines, and the reference source lines,
- wherein the second memory cell array is configured to generate a plurality of reference currents;
- and
- an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals based on the plurality of reference currents.
16 more elements
A neuromorphic device comprising:
- a memory cell array comprising:
- first resistive memory cells connected to word lines, bit lines, and source lines,
- second resistive memory cells connected to the word lines, at least one redundancy bit line, and at least one redundancy source line, and
- third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines,
- wherein the memory cell array is configured to store weight data corresponding to a weight of a neural network in the first resistive memory cells, and generate a plurality of read currents based on input signals and the weight data;
- and
- an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.
4 more elements
Dependencies are inferred from the claim text.