Non-volatile electro-optical high-bandwidth ultra-fast large-scale memory architecture

A memory array including a plurality of memory cells arranged with rows of memory cells and columns of memory cells, each memory cell including:

• a voltage divider that outputs an output voltage, the voltage divider comprising:
• a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component;
• and
• a switchable magnetic tunnel junction including a free magnet and a fixed magnet, the reference resistive device and the switchable magnetic tunnel junction arranged in series, the switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light;
• a switching component configured to activate the voltage divider for memory write operations, the switching component in series with the voltage divider, wherein there is an applied voltage applied across the combination of the voltage divider and the switching component;
• and
• a light modulator in electrical communication with the output voltage, the light modulator configured to modulate a guided light beam for memory write operations.

A memory array comprising:

• an array of memory components arranged in rows of memory cells and columns of memory cells, each column including:
• a reference resistive device;
• and
• a plurality of memory cell components, each memory cell component including:
• a switchable magnetic tunnel junction including a free magnet and a fixed magnet, the reference resistive device and the switchable magnetic tunnel junction arranged in series, the switchable magnetic tunnel junction configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light, wherein the reference resistive device and a selected switchable magnetic tunnel junction form a voltage divider that provides an output voltage;
• a switching component configured to activate the voltage divider for memory read and write operations, the switching component in series with the voltage divider;
• and
• a light modulator in electrical communication with the output voltage, the light modulator configured to modulate guided light for memory read operations,
• wherein each switching component of each row of memory cell components is in electrical communication with the same control signal so that a row of memory cell components can be simultaneously selected.

An ultrafast non-volatile memory cell for wafer-scale integration comprising:

• a voltage divider that outputs an output voltage, the voltage divider comprising:
• a reference resistive device that is a reference magnetic tunnel junction or another reference resistive component;
• and
• a switchable SOT device including a free magnet and a fixed magnet which are disposed over an SOT layer, the SOT layer having a first SOT terminal and a second SOT terminal, the reference resistive device and the switchable SOT device arranged in series, the switchable SOT device is configured such that the free magnet is light switchable between a high impedance state and a low impedance state upon application of an electric signal and incident light;
• a first transistor switch in electrical communication with the first SOT terminal, the first transistor switch having a first junction end and a second junction end, the second junction end being in direct electrical communication with the first SOT terminal;
• a second transistor switch in electrical communication with the reference resistive device, the second transistor switch having a third junction end and a fourth junction end, the third junction end being in direct electrical communication with the reference resistive device that;
• and
• a light modulator in electrical communication with the output voltage, the light modulator configured to modulate a guided light beam for memory write operations.