Vector processor architectures

A vector processing system comprising:

• a plurality of vector registers configurable to store a plurality of vectors;
• first switch circuitry communicatively coupled to the plurality of vector registers, wherein the first switch circuitry is configurable to receive the plurality of vectors directly from the plurality of vector registers and route a portion of the plurality of vectors to a plurality of vector processing units, wherein the plurality of vector processing units respectively comprise second switch circuitry configurable to route data within the plurality of vector processing units and are communicatively coupled to the first switch circuitry and configurable to:
• receive the portion of the plurality of vectors directly from the first switch circuitry;
• perform one or more operations involving the portion of the plurality of vectors;
• and
• output a second plurality of vectors generated by performing the one or more operations;
• and
• third switch circuitry communicatively coupled to the plurality of vector processing units and the plurality of vector registers, wherein the third switch circuitry is configurable to:
• receive the second plurality of vectors directly from the plurality of vector processing units;
• and
• route the second plurality of vectors to the plurality of vector registers.

A programmable logic device, comprising:

• one or more memory blocks configurable to store a plurality of vectors;
• first routing circuitry communicatively coupled to the one or more memory blocks, wherein the first routing circuitry is configurable to receive the plurality of vectors directly from the one or more memory blocks and route a portion of the plurality of vectors to a vector compute unit to be used to execute an instruction, wherein the vector compute unit is communicatively coupled to the first routing circuitry, and wherein the vector compute unit comprises one or more vector processing units, wherein the one or more vector processing units respectively comprise second routing circuitry to route data within the one or more vector processing units configurable to execute the instruction by:
• receiving the portion of the plurality of vectors directly from the first routing circuitry;
• perform one or more operations involving the portion of the plurality of vectors;
• and
• output one or more vectors generated by performing the one or more operations;
• and
• third routing circuitry communicatively coupled to the one or more vector processing units and the one or more memory blocks, wherein the third routing circuitry is configurable to:
• receive the one or more vectors directly from the one or more vector processing units;
• and
• route the one or more vectors to the one or more memory blocks.