Memory device interface and method

A memory system comprising:

• a plurality of stacked dynamic random access memory (DRAM) die;
• and
• a buffer die coupled to the plurality of stacked DRAM die and configured to couple to a processor, the buffer die comprising:
• a processor device interface configured to communicate data with the processor at a first data transfer rate;
• a first sub-channel DRAM interface coupled to the processor device interface and a first DRAM die of the plurality of stacked DRAM die, wherein the first sub-channel DRAM interface is configured to communicate data with the first DRAM die at a second data transfer rate;
• and
• a second sub-channel DRAM interface coupled to the processor device interface and a second DRAM die of the plurality of stacked DRAM die;
• wherein the buffer die is configured to map data between the processor and the first DRAM die and the second DRAM die of the plurality of stacked DRAM die.

A memory system comprising:

• a buffer die configured to couple to a processor;
• and
• a plurality of stacked dynamic random access memory (DRAM) die coupled to the buffer die, wherein the plurality of stacked DRAM die comprises one of:
• vertically aligned stacked DRAM die comprising a plurality of through silicon vias (TSVs) coupling the plurality of stacked DRAM die to the buffer die;
• or
• stair-stepped stacked DRAM die having one or more than one step directions within a single stack, wherein a first wire bond is coupled to the buffer die and a first DRAM die of the plurality of stacked DRAM die.