Error correction systems and methods
AssigneeMicrosoft Technology Licensing, LLC
InventorGregory Alan Bryant
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure include techniques for error correction. Multiple successive odd syndromes are generated from input data comprising parity bits. Coefficients are generated and applied to a finite element field to detect multiple bit errors. Error correction circuitry corrects detected error bits. A single bit error detector may detect single bit errors. The error correction circuit may select between a single bit error vector and a multibit error vector based on one of the coefficients. The circuitry may be implemented in combinational logic to perform detection and correction in a single clock cycle.
Claims20
An electronic circuit for correcting data errors comprising:
- a syndrome generator to receive data comprising a plurality of parity bits and generate a plurality of successive odd syndromes;
- a coefficient generator, configured to receive the plurality of successive odd syndromes and combine the syndromes to produce a plurality of coefficients;
- a multibit error detector configured to receive the coefficients, wherein the coefficients are applied to a plurality of digital values, wherein the digital values applied to the plurality of coefficients generates a first bit error vector;
- an error correction circuit configured to combine the first bit error vector with the data, wherein the first bit error vector is combined with the data to correct one or more bit errors in the data
- a single bit error detector configured to receive a first syndrome of the plurality of successive odd syndromes and produce a second bit error vector, wherein the error correction circuit combines the second bit error vector with the data to correct one bit error in the data;
- and
- the error correction circuit configured to combine the first bit error vector with the data, wherein the first bit error vector is combined with the data to correct one or more bit errors in the data, wherein one of the plurality of coefficients selects between the first bit error vector and the second bit error vector in the error correction circuit.
A method of correcting data errors comprising:
- receiving data comprising a plurality of parity bits and generating a plurality of successive odd syndromes;
- receiving the plurality of successive odd syndromes and combining the syndromes to produce a plurality of coefficients;
- applying the plurality of coefficients to a plurality of digital values, wherein the digital values applied to the plurality of coefficients generate a first bit error vector;
- and
- receiving a first syndrome of the plurality of successive odd syndromes and produce a second bit error vector, wherein an error correction circuit combines the second bit error vector with the data to correct one bit error in the data;
- combining the first bit error vector with the data, wherein the first bit error vector is combined with the data to correct one or more bit errors in the data;
- wherein one of the plurality of coefficients selects between the first bit error vector and the second bit error vector in the error correction circuit.
Dependencies are inferred from the claim text.