Apparatus and method for wideband multi-phase clock generation
AssigneeCiena Corporation
InventorsJacob Pike, Naim Ben-Hamida, Jerry Yee-Tung Lam, Euhan Chong, David Berton
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Abstract
Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.
Claims20
An inner clock generation circuit, comprising:
- a selectable frequency divider, comprising:
- a ring of tri-state inverters;
- a reset gate on an output of each tri-state inverter in the ring;
- and
- a reset circuit comprising one or more selectable flip-flops;
- and
- a duty-cycle limiter that generates clock signals having a duty cycle less than 100% from three out of four quadrature clock signals.
A method for creating a deterministic starting state of a ring-based injection locked frequency divider in an inner clock generation circuit, comprising:
- implementing a reset gate on an output of each tri-state inverter in a ring of tri-state inverters;
- implementing a reset circuit comprising one or more selectable flip-flops;
- applying a reset signal to each reset gate, wherein the reset gate forces the output of the tri-state inverter to a starting state;
- and
- applying a phase select signal to the reset circuit, wherein the reset circuit inverts the output of the tri-state inverter.
An inner clock generation circuit, comprising:
- a central phase-locked loop;
- a clock and data recovery component coupled to the central phase-locked loop configured to generate two phases of clock signals;
- a selectable frequency divider coupled to the clock and data recovery component configured to generate quadrature clock signals, comprising:
- a ring of tri-state inverters;
- a reset gate on an output of each tri-state inverter in the ring;
- and
- a reset circuit comprising one or more selectable flip-flops;
- a multiphase clock generator coupled to the selectable frequency divider;
- a deskew stage coupled to the multiphase clock generator, wherein the multiphase clock generator and the deskew stage are configured to generate sixteen phases of clock signals;
- a duty-cycle limiter coupled to the deskew stage and a rank 1 track and hold sampling circuit, wherein the duty-cycle limiter generates clock signals having a 25% duty cycle from three out of four quadrature clock signals out of the sixteen phases of clock signals;
- and
- a rank 2 phase rotator coupled to the deskew stage and a rank 2 track and hold sampling circuit.
Dependencies are inferred from the claim text.