US 12,249,626 B2 · Arsenic diffusion profile engineering for transistors

Abstract

Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

Claims20

Dependent claims

A transistor, comprising:

a gate electrode structure disposed over a channel region;
a source/drain extension region doped with arsenic disposed adjacent to the channel region;
an epitaxial arsenic doped silicon layer disposed on the source/drain extension region;
and
an epitaxial source/drain region disposed on the epitaxial arsenic doped silicon layer, the arsenic doped silicon layer disposed between the source/drain region and the source/drain extension region.

2 more elements

Dependencies are inferred from the claim text.

Arsenic diffusion profile engineering for transistors

Life of this patent

Arsenic diffusion profile engineering for transistors

Life of this patent

Abstract

Claims20