Integrated circuit device, method, layout, and system

A current mode logic (CML) circuit comprising:

• a first resistor comprising a first source/drain (S/D) metal portion extending in a first direction directly on a first dielectric layer located between a first pair of gate structures of a first row of gate structures aligned in a second direction perpendicular to the first direction;
• a second resistor comprising a second S/D metal portion extending in the first direction directly on a second dielectric layer located between a second pair of gate structures of the first row of gate structures;
• a first transistor comprising a first gate structure of a second row of gate structures, first and second S/D structures, a third S/D metal portion aligned with the first S/D metal portion in the first direction and positioned on the first S/D structure, and a fourth S/D metal portion on the second S/D structure;
• a second transistor comprising a second gate structure of the second row of gate structures, the second S/D structure, the fourth S/D metal portion, a third S/D structure, and a fifth S/D metal portion aligned with the second S/D metal portion in the first direction and positioned on the third S/D structure;
• a third transistor comprising a first gate structure of a third row of gate structures, fourth and fifth S/D structures, a sixth S/D metal portion on the fourth S/D structure, and a seventh S/D metal portion on the fifth S/D structure;
• and
• a fourth transistor comprising a second gate structure of the third row of gate structures, the fifth S/D structure, the seventh S/D metal portion, a sixth S/D structure, and an eighth S/D metal portion on the sixth S/D structure,
• wherein
• the first resistor and first, third and fourth transistors are coupled in series,
• the second resistor and second, third, and fourth transistors are coupled in series, and
• the first through eighth S/D metal portions are in a same layer and extend above each of the gate structures in a third direction perpendicular to each of the first and second directions.

An integrated circuit (IC) device comprising:

• a load resistor section comprising:
• a first resistor comprising a first source/drain (S/D) metal portion extending in a first direction directly on a first dielectric layer located between a first pair of gate structures in a first row of gate structures aligned in a second direction perpendicular to the first direction;
• and
• a second resistor comprising a second S/D metal portion extending in the first direction directly on a second dielectric layer located between a second pair of gate structures in the first row of gate structures;
• a switching transistor section comprising:
• a first transistor comprising third and fourth S/D metal portions adjacent to a first gate structure in a second row of gate structures, wherein the third S/D metal portion is aligned with the first S/D metal portion in the first direction and coupled to a first terminal of the first resistor;
• and
• a second transistor comprising fifth and sixth S/D metal portions adjacent to a second gate structure in the second row of gate structures, wherein the fifth S/D metal portion is aligned with the second S/D metal portion in the first direction and coupled to a first terminal of the second resistor;
• and
• a transistor stack section comprising:
• a plurality of transistors comprising a third transistor comprising seventh and eighth S/D metal portions adjacent to a first gate structure in a third row of gate structures, wherein the seventh S/D metal portion is coupled to each of the fourth and sixth S/D metal portions,
• wherein each of the first through eighth S/D metal portions is positioned in a same layer and extends above each of the gate structures in a third direction perpendicular to each of the first and second directions.