Back to results
US 12,249,371 B2Granted
Reconfigurable in-memory physically unclonable function
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Feng Kao, Katherine H. Chiang
Life of this patent
Estimating the term…
Abstract
A physically unclonable function (PUF) device includes first and second inverters, each of which includes a common gate node and a common drain node. The common drain node of the first inverter is electrically connected to the common gate node of the second inverter. The PUF device also includes a common output node, a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node, and a second RMD electrically connected to the common drain node of the second inverter and the common output node.
Claims20
A physically unclonable function (PUF) device, comprising:
- first and second inverters, each of the first and second inverters comprising:
- a common gate node;
- and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter, and wherein the first and second inverters are connected in series between the common gate node of the first inverter and the common drain node of the second inverter and configure to induce a voltage change at the common drain node of the second inverter by a voltage change at the common gate node of the first inverter through a voltage change at the common drain node of the first inverter;
- a common output node;
- a first resistive memory device (RMD) electrically connected directly to the common drain node of the first inverter and directly to the common output node;
- and a second RMD electrically connected directly to the common drain node of the second inverter and directly to the common output node, wherein the first inverter is configured to receive a programming voltage and the common output node is configured to float in a randomized programming operation.
3 more elements
A physically unclonable function (PUF) device, comprising:
- first through fifth inverters connected in series, each of the first through fifth inverters comprising:
- a common gate node;
- and a common drain node, wherein the common drain nodes of the first through fourth inverters are electrically connected to the common gate nodes of the respective second through fifth inverters;
- first through fourth common output nodes;
- and first through eighth resistive memory devices (RMDs), wherein the first and second RMDs are electrically connected directly to the first common output node and directly to the common drain nodes of the respective first and second inverters, the third and fourth RMDs are electrically connected directly to the second common output node and directly to the common drain nodes of the respective second and third inverters, the fifth and sixth RMDs are electrically connected directly to the third common output node and directly to the common drain nodes of the respective third and fourth inverters, and the seventh and eighth RMDs are electrically connected directly to the fourth common output node and directly to the common drain nodes of the respective fourth and fifth inverters, wherein the first inverter is configured to receive a programming voltage and the first through fourth common output nodes are configured to float in a randomized programming operation.
2 more elements
A physically unclonable function (PUF) device, comprising:
- first and second inverters connected in series, each of the first and second inverters comprising:
- a common gate node;
- and a common drain node, wherein the common drain node of the first inverter is electrically connected to the common gate node of the second inverter;
- a common output node;
- a first resistive memory device (RMD) electrically connected to the common drain node of the first inverter and the common output node;
- and a second RMD electrically connected to the common drain node of the second inverter and the common output node, wherein in a first programming operation, the PUF device is configured to apply a first voltage to each of the common gate node of the first inverter and the common output node, in a second programming operation, the PUF device is configured to apply a second voltage to the common gate node of the first inverter and a third voltage to the common output node, in a randomized programming operation, the PUF device is configured to apply a fourth voltage to the common gate node of the first inverter and float the common output node, and in a read operation, the PUF device is configured to apply a fifth voltage to the common gate node of the first inverter and output a measurement voltage from the common output node.
3 more elements
Dependencies are inferred from the claim text.