Back to results
US 12,249,370 B2Granted
Systems and techniques for accessing multiple memory cells concurrently
AssigneeMicron Technology, Inc.
InventorFederico Pio
Life of this patent
Estimating the term…
Abstract
Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.
Claims22
A method, comprising:
- identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity, wherein the memory tile includes more than one deck of memory cells;
- identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity;
- reading the first memory cell;
- and
- reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.
2 more elements
A method, comprising:
- identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity;
- identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity, and wherein the first polarity is opposite the second polarity such that the first section of memory cells is configured to be read with a positive polarity read pulse and the second section of memory cells is configured to read with a negative polarity read pulse;
- reading the first memory cell;
- and
- reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.
2 more elements
A method, comprising:
- identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity, and wherein a memory cell of the memory tile comprises a chalcogenide material having a non-uniform distribution of ions to indicate a logic state of one memory cell of the first section of memory cells;
- identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity;
- reading the first memory cell;
- and
- reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.
2 more elements
A method, comprising:
- identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity;
- identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity, and wherein one or more trim parameters for the first section of memory cells are independent of one or more trim parameters for the second section of memory cells;
- reading the first memory cell;
- and
- reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.
2 more elements
An electronic memory apparatus, comprising:
- a memory tile having a first section of memory cells and a second section of memory cells, wherein the memory cells of the first section are configured to be read in response to application of a first read pulse having a first polarity and the memory cells of the second section are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity;
- a first sense component coupled with the first section of memory cells of the memory tile and configured to identify a logic state of one memory cell of the first section of memory cells based at least in part on the first read pulse having the first polarity;
- and
- a second sense component coupled with the second section of memory cells of the memory tile and configured to identify the logic state of one memory cell of the second section of memory cells based at least in part on the second read pulse having the second polarity.
1 more element
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
- identify a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity, wherein the memory tile includes more than one deck of memory cells;
- identify a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity;
- read the first memory cell;
- and
- read the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.
2 more elements
Dependencies are inferred from the claim text.