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US 12,248,782 B2Granted
Accelerating processor based artificial neural network computation
AssigneeInfineon Technologies AG
InventorsAndrew Stevens, Wolfgang Ecker, Sebastian Prebeck
Life of this patent
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Abstract
An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.
Claims20
A method for an artificial neural network (ANN), comprising:
- determining, via a memory fetch device, a stream of addresses of packed data stored on a memory device and a suppression indicator, wherein the suppression indicator identifies a subset of addresses in the stream of addresses that are associated with generated packed data on the memory device;
- fetching, via the memory fetch device, stored packed data from the memory device based on the stream of addresses and the suppression indicator, wherein the memory fetch device fetches the stored packed data from the memory device sequentially, wherein the memory fetch device processes the stored packed data sequentially;
- generating, via the memory fetch device, generated data based on the suppression indicator;
- and
- constructing, via the memory fetch device, formatted data from the stored packed data or the generated packed data based on a predefined data structure of a microcontroller.
2 more elements
An apparatus employed in a processing device comprising:
- a processor configured to process data of a predefined data structure, wherein the processor has as a single-issue microarchitecture and comprises special-function registers, bus agents, and an instruction fetch device;
- a memory fetch device coupled to the processor, wherein the memory fetch device is configured as a sequential state-machine and is configured to:
- determine addresses of packed data for the processor, wherein the packed data is stored on a memory device that is coupled to the processor;
- fetch the packed data at least partially from an instruction memory;
- share resources with the instruction fetch device, the special-function registers, and the bus agents of the processor, wherein the instruction fetch device is configured to fetch the instruction memory;
- and
- provide output data based on the addresses of the packed data to the processor, wherein the output data is configured according to the predefined data structure, wherein the memory fetch device is configured to process the packed data sequentially.
4 more elements
An apparatus for an artificial neural network (ANN) comprising:
- a microcontroller, configured to be coupled to a memory device and configured to process a data stream, wherein the data stream is configured to match at least one of a predefined precision, predefined layout or predefined data structure;
- a data streaming fetch device, coupled to the memory device and the microcontroller, configured to process packed data on the memory device and provide a continuous output stream to the microcontroller, wherein the packed data comprises stored packed data and generated packed data, wherein the generated packed data is present in the packed data based on a predefined packing format of the packed data, wherein the data streaming fetch device is configured to process the packed data sequentially, wherein the data streaming fetch device comprises:
- an address generator component configured to generate a stream of addresses and sub-word data-item information of the packed data, wherein the sub-word data-item information includes sub-word item numbers and sub-word item positions of the stored packed data on the memory device and associated with the stream of addresses;
- a data fetch component configured to selectively fetch the stored packed data and selectively suppress a fetch of the generated packed data from the memory device based on the stream of addresses and the sub-word data-item information;
- and
- a data formatting component configured to provide the continuous output stream to the microcontroller.
3 more elements
Dependencies are inferred from the claim text.