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US 12,248,021 B2Granted
Debug trace microsectors
AssigneeAltera Corporation
InventorsSean R. Atsatt, Ilya K. Ganusov
Life of this patent
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Abstract
Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
Claims13
An integrated circuit, comprising:
- a first network-on-chip disposed around at least a partial perimeter of a plurality of microsectors arranged in a row and column grid;
- and
- a first microsector of the plurality of microsectors, wherein the first microsector is coupled to a first row controller, the first microsector comprising:
- a plurality of logic access blocks, each logic access block coupled to a respective one of a plurality of data registers;
- a plurality of routing blocks, each routing block comprising a first highly pipelined (HIPI) register chain and a second HIPI register chain, wherein at least one of the plurality of data registers is coupled to at least one of the first HIPI register chain and second HIPI register chain;
- and
- a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller and a second shift register chain configurable to shift data into the first microsector from the first row controller.
4 more elements
A system, comprising:
- programmable logic circuitry comprising configuration memory, the programmable logic circuitry comprising:
- a first microsector, wherein the first microsector is coupled to a first row controller, the first microsector comprising:
- a plurality of logic access blocks, each logic access block coupled to a respective one of a plurality of data registers;
- a plurality of routing blocks, each routing block comprising a first highly pipelined (HIPI) register chain and a second HIPI register chain, wherein at least one of the plurality of data registers is coupled to at least one of the first HIPI register chain and the second HIPI register chain;
- and
- a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller;
- and
- a first control circuitry of the first row controller, wherein the first control circuitry is configured to receive data from the first shift register chain.
5 more elements
Dependencies are inferred from the claim text.