Iterative error correction in memory systems

A non-transitory computer-readable medium storing instructions that, when executed by one or more processors of a computer system, perform a method for memory error detection and recovery in a decoding system, the method comprising:

• receiving, into a first decoder within the decoding system, a memory transfer block (MTB) (i) comprising data and parity information and having (ii) a vertical portion and a horizontal portion;
• performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder;
• and
• upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder;
• wherein the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.

An apparatus comprising:

• a decoding system configured to receive a memory transfer block (MTB) (i) comprising data and parity information and (ii) having a vertical portion and a horizontal portion, the decoding system comprising:
• a first decoder including binary hamming code logic configured to perform error detection and correction on the vertical portion of the MTB;
• and
• a second decoder including non-binary hamming code logic configured to perform error detection and correction on the horizontal portion of the MTB;
• wherein upon performing error detection and correction in the first decoder on the vertical portion of the MTB, then forwarding MTB to the second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB,
• wherein the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.