Alias rejection in analog-to-digital converters (ADCs)
AssigneeQUALCOMM Incorporated
InventorBehnam Sedighi
Life of this patent
Estimating the term…
Abstract
Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.
Claims40
An analog-to-digital converter (ADC) circuit comprising:
- a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit;
- and
- a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit, wherein the second circuit portion comprises an analog finite impulse response (FIR) filter operated at the second clock rate.
An analog-to-digital converter (ADC) circuit comprising:
- a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit;
- and
- a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit, wherein the ADC circuit comprises a pipelined ADC having a plurality of stages, wherein the second circuit portion comprises one or more initial stages in the plurality of stages of the pipelined ADC and wherein the first circuit portion comprises one or more latter stages in the plurality of stages of the pipelined ADC.
An analog-to-digital converter (ADC) circuit comprising:
- a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit;
- and
- a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit, wherein:
- the ADC circuit comprises a successive-approximation register (SAR) ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator, the multi-input comparator having a plurality of inputs coupled to outputs of the plurality of CDACs;
- the second circuit portion comprises the plurality of CDACs;
- and
- the first circuit portion comprises the multi-input comparator.
An analog-to-digital converter (ADC) circuit comprising:
- a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit;
- and
- a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit, wherein the second clock rate is two times the sampling rate of the ADC circuit.
A method of signal conversion, the method comprising converting, using an analog-to-digital converter (ADC) circuit, an analog signal to a digital signal at a sampling rate of the ADC circuit, wherein the converting comprises:
- operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit;
- and
- operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit, wherein operating the second circuit portion comprises operating an analog finite impulse response (FIR) filter in the second circuit portion of the ADC circuit at the second clock rate.
A method of signal conversion, the method comprising converting, using an analog-to-digital converter (ADC) circuit, an analog signal to a digital signal at a sampling rate of the ADC circuit, wherein the converting comprises:
- operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit;
- and
- operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit, wherein the ADC circuit comprises a pipelined ADC having a plurality of stages, wherein the second circuit portion comprises one or more initial stages in the plurality of stages of the pipelined ADC, and wherein the first circuit portion comprises one or more latter stages in the plurality of stages of the pipelined ADC.
A method of signal conversion, the method comprising converting, using an analog-to-digital converter (ADC) circuit, an analog signal to a digital signal at a sampling rate of the ADC circuit, wherein the converting comprises:
- operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit;
- and
- operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit, wherein:
- the ADC circuit comprises a successive-approximation register (SAR) ADC having a plurality of capacitive digital-to-analog converters (CDACs) and a multi-input comparator, the multi-input comparator having a plurality of inputs coupled to outputs of the plurality of CDACs;
- the second circuit portion comprises the plurality of CDACs;
- and
- the first circuit portion comprises the multi-input comparator.
A method of signal conversion, the method comprising converting, using an analog-to-digital converter (ADC) circuit, an analog signal to a digital signal at a sampling rate of the ADC circuit, wherein the converting comprises:
- operating a first circuit portion of the ADC circuit at a first clock rate equal to the sampling rate of the ADC circuit;
- and
- operating a second circuit portion of the ADC circuit at a second clock rate higher than the sampling rate of the ADC circuit, wherein the second clock rate is more than two times the sampling rate of the ADC circuit.
Dependencies are inferred from the claim text.