Electronic integrator circuit for driving inductor

An apparatus comprising:

• a first transistor comprising a first gate, a first drain and a first source;
• a second transistor comprising a second gate and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source;
• a third transistor comprising a third gate and a third source, the third gate coupled to the first drain, and the third source coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp;
• and
• a first capacitor coupled between the third source and the second gate, wherein the sampled voltage is held on a second capacitor coupled to a replica gate of a replica transistor, the replica gate switchably connected to the second gate with a first switch, and a replica drain of the replica transistor coupled to a current mirror, the current mirror coupled to the second current source.

An apparatus comprising:

• a first transistor comprising a first gate, a first drain and a first source;
• a second transistor comprising a second gate and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source;
• a third transistor comprising a third gate and a third source, the third gate coupled to the first drain, and the third source coupled to a load, wherein the third transistor is configured to source a load current to the load in response to an integration of the linear current ramp;
• and
• a first capacitor coupled between the third source and the second gate, wherein the sampled voltage is held on a second capacitor coupled to a replica gate of a replica transistor, the replica gate switchably connected to the second gate with a first switch, and a replica drain of the replica transistor coupled to a current mirror, the current mirror coupled to the second current source, and wherein the second gate is switchably coupled to a voltage supply with a second switch prior to the integration.