Method of operating a storage device

A storage device comprising:

• a first AND logic gate comprising a first input configured to be coupled to a first third-party device to receive a first selection signal, a second input configured to be coupled to the first third-party device to receive a first status signal, and an output configured to transmit a first output signal when the first selection signal and the first status signal are received;
• a second AND logic gate comprising a first input configured to be coupled to a second third-party device to receive a second selection signal, a second input configured to be coupled to the second third-party device to receive a second status signal, and an output configured to transmit a second output signal when the second selection signal and the second status signal are received;
• a first OR logic gate comprising a first input coupled to the output of the first AND logic gate, a second input coupled to the output of the second AND logic gate, and an output;
• a selection circuit comprising a first control input configured to be coupled to receive the first select signal of the first third-party device, a second control input configured to be coupled to receive the second select signal of the second third-party device, a first data input configured to be coupled to receive a first data signal of the first third-party device, a second data input configured to be coupled to receive a second data signal of the second third-party device;
• a first D latch comprising an activation input coupled to the output of the first OR logic gate and a data input coupled to an output of the selection circuit to receive the first data signal from the first third-party device or the second data signal from the second third-party device;
• and
• a second D latch comprising an activation input coupled to the output of the first OR logic gate and a data input coupled to the output of the selection circuit to receive the first data signal from the first third-party device or the second data signal from the second third-party device.

A device comprising:

• a first AND logic gate comprising a first input, a second input, and an output;
• a second AND logic gate comprising a first input, a second input, and an output;
• a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate;
• a first selection circuit having first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate;
• a first D latch comprising a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate;
• a second D latch comprising a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate;
• a third AND logic gate comprising a first input, a second input, and an output;
• a fourth AND logic gate comprising a first input, a second input, and an output;
• a second OR logic gate comprising a first input coupled to the output of the third AND logic gate and a second input coupled to the output of the fourth AND logic gate;
• a second selection circuit having first and second data inputs, a first control input coupled to the first input of the third AND logic gate and a second control input coupled to the first input of the fourth AND logic gate;
• a third D latch comprising a data input coupled to an output of the second selection circuit and an activation input coupled to an output of the second OR logic gate;
• and
• a fourth D latch comprising a data input coupled to the output of the second selection circuit and an activation input coupled to the output of the second OR logic gate;
• a fifth D latch comprising a data input coupled to an output of the first D latch;
• a sixth D latch comprising a data input coupled to an output of the second D latch;
• a seventh D latch comprising a data input coupled to an output of the third D latch;
• and
• an eighth D latch comprising a data input coupled to an output of the fourth D latch.