Circuit and method to enhance efficiency of semiconductor device

A method, comprising:

• providing an operational amplifier, having a first input terminal, a second input terminal, a first output terminal and a second output terminal;
• providing a plurality of input capacitors, having a first input capacitor and a second input capacitor;
• providing a plurality of output capacitors, having a first output capacitor and a second output capacitor;
• providing a plurality of sampling switches, having a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch;
• providing a plurality of holding switches, having a first holding switch and a second holding switch;
• and
• providing a plurality of combined switches, having a first combined switch and a second combined switch,
• wherein the first sampling switch comprises two ends directly coupled to the first input terminal and the first holding switch, respectively, the second sampling switch comprises two ends directly coupled to the second input terminal and the second holding switch, respectively, the third sampling switch comprises two ends directly coupled to the first output capacitor and a first output end, respectively, and the fourth sampling switch comprises two ends directly coupled to second output capacitor and a second output end, respectively.

A method of operating a circuit, comprising:

• providing an operational amplifier, having a first input terminal, a second input terminal, a first output terminal and a second output terminal;
• providing a plurality of input capacitors, having a first input capacitor and a second input capacitor;
• providing a plurality of output capacitors, having a first output capacitor and a second output capacitor;
• providing a plurality of sampling switches, having a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch, the plurality of sampling switches operated according to a sampling cycle of a data clock;
• providing a plurality of holding switches, having a first holding switch and a second holding switch operated according to a holding cycle of the data clock;
• and
• providing a plurality of combined switches, having a first combined switch and a second combined switch operated according to a combined clock,
• wherein the first combined switch comprises two ends coupled to the first input capacitor and the first output capacitor, respectively, and the second combined switch comprises two ends coupled to the second input capacitor and the second output capacitor, respectively,
• wherein the first sampling switch comprises two ends coupled to the first input terminal and the first output terminal, respectively, the second sampling switch comprises two ends coupled to the second input terminal and the second output terminal, respectively, the third sampling switch comprises two ends directly coupled to the first output capacitor and a first output end, respectively, and the fourth sampling switch comprises two ends coupled to second output capacitor and a second output end,
• wherein the first holding switch comprises two ends coupled to the first sampling switch and the third sampling switch, respectively, and the second holding switch comprises two ends coupled to the second sampling switch and the fourth sampling switch, respectively;
• during a first phase, setting the sampling cycle at a high level and the combined clock at a low level;
• during a second phase, setting the sampling cycle at a high level and the combined clock at a high level;
• during a third phase, setting the holding cycle at a low level and the combined clock at a low level;
• and
• during a fourth phase, setting the holding cycle at a low level and the combined clock at a high level.