US 12,243,933 B2 · Semiconductor device layouts

Abstract

A semiconductor device with an active transistor cell comprising a p-type first and second base layers, surrounding an n-type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional gate runners formed adjacent to the first base layer, outside the active cell, and contacting the first gate electrodes at the cross points thereof. The additional gate runners do not affect the active cell design in terms of cell pitch i.e., the design rules for cell spacing, hole drainage between the cells, or gate-collector capacitance, hence resulting in optimum low conduction and switching losses. The transistor cell and layout designs offer a range of advantages both in terms of performance and manufacturability, with the potential of applying additional layers or structures.

A semiconductor transistor cell with a first surface and a second surface, wherein a first contact electrode is operatively connected to the first surface and a second contact electrode is operatively connected to the second surface, comprising:

a drift layer of a first conductivity type located between the first surface and the second surface;
a source region of the first conductivity type operatively connected to the first contact electrode, with a doping concentration greater than a doping concentration of the drift layer, with edges defined by a closed form in a top plane view;
a first base layer of a second conductivity type, opposite of the first conductivity type, extending in the drift layer below the source region, and extending in the top plane view beyond the edges of the source region;
a second base layer of the second conductivity type embedded within the first base layer and extending in the drift layer under the source region, having a doping concentration greater than a doping concentration of the first base layer, operatively connected to the first contact electrode via a contact opening;
a plurality of trench regions with trench recesses formed on the first surface of the drift layer, each trench recess comprising a first gate electrode and a first insulating layer, the first insulating layer electrically insulating the first gate electrode from the second base layer, the source region and the drift layer;
wherein at least one trench region abuts the source region;
a second insulating layer on the first surface of the drift layer in contact with the first base layer, the source region and the drift layer, wherein a singular point is defined on each lateral trench wall of each trench region abutting the source region at the intersection between the first surface of the source region, and the edge of the second insulating layer abutting the said lateral trench wall;
a gate runner on the first surface of the drift layer, in contact with at least one of a plurality of first gate electrodes;
and
a third insulating layer, electrically insulating the first contact electrode from the first gate electrodes and the gate runner;
wherein the first insulating layer and the first base layer are configured to form MOS channels only on those respective lateral trench walls of the plurality of trench regions abutting the source region wherein a width of each of the MOS channels is equivalent to a segment of a circle arranged on the lateral trench walls of the plurality of trench regions and centered on the singular point adjacent to the respective lateral trench walls,
wherein in the top plane view, the source region, the first base layer and the second base layer are shaped as polygons and the plurality of trench regions extend longitudinally:
at an angle of 90 degrees with respect to the sides of the said polygons;
or
along the diagonals and intersecting the corners of the said polygons;
wherein the gate runner is formed:
with trench recesses embedding a conductive electrode and an insulating layer, or
as a planar conductive electrode on the first surface and separated from the drift layer by an insulating layer.

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Semiconductor device layouts

Life of this patent

Semiconductor device layouts

Life of this patent

Abstract

Claims19