Programmable inductor and methods of manufacture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Mirng-Ji Lii, Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Nien-Fang Wu
Life of this patent
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Abstract
A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a first conductive turn in physical contact with a first via and a second via;
- and
- forming a second conductive turn in physical contact with a third via and a fourth via, wherein the first conductive turn and the second conductive turn are individually connected to two fuses, wherein a first one of the two fuses is misaligned from a second one of the two fuses, wherein the first via is adjacent to a first plurality of vias in physical contact with the first conductive turn, wherein the second via is adjacent to a second plurality of vias in physical contact with the first conductive turn, and wherein the third via is adjacent to a third plurality of vias in physical contact with the second conductive turn.
A method of manufacturing a semiconductor device, the method comprising:
- forming a first fuse connected to a first via and a second via;
- forming a second fuse connected to a third via and a fourth via;
- and
- forming a third fuse connected to a fifth via and a sixth via, wherein each of the first fuse, the second fuse, and the third fuse are connected to at least two of a plurality of conductive turns, wherein at least one of the first fuse, the second fuse, and the third fuse are misaligned from each other in a top down view, wherein the first fuse is connected to a first plurality of vias and a second plurality of vias, wherein the first via is one of the first plurality of vias and wherein the second via is one of the second plurality of vias, and wherein the third fuse is connected to a third plurality of vias and a fourth plurality of vias, wherein the third plurality of vias has a different number of vias than the first plurality of vias.
A method of manufacturing a semiconductor device, the method comprising:
- depositing a first conductive turn in physical contact with at least a first via and a second via, the first via connecting the first conductive turn to a first fuse and the second via connecting the first conductive turn to a second fuse;
- and
- depositing a second conductive turn in physical contact with at least a third via and a fourth via, the third via connecting the second conductive turn to the second fuse and the fourth via connecting the second conductive turn to a third fuse, the first fuse aligned to have a longitudinal axis which intersects a longitudinal axis of the second fuse, wherein the at least the first via is part of a first plurality of vias in contact with the first conductive turn, and wherein the at least the third via is part of a second plurality of vias in contact with the second conductive turn, the second plurality of vias having a different number of vias than the first plurality of vias.
Dependencies are inferred from the claim text.