Single ended sense amplifier with current pulse circuit
AssigneeGlobalFoundries U.S. Inc.
InventorsSiva Kumar Chinthu, Suresh Pasupula, Devesh Dwivedi, Chunsung Chiang
Life of this patent
Estimating the term…
Abstract
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
Claims19
A memory circuit, comprising:
- a bit cell having a resistor configurable to a low resistive state and a high resistive state;
- a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to a data path of the bit cell;
- and
- a NAND gate having an output coupled to a gate of the PMOS device, wherein a first input of the NAND gate is controlled by a state of the bit cell;
- wherein the memory circuit is embodied in one of a resistive random access memory (RRAM) or a Magnetoresistive random-access memory (MRAM).
A sense amplifier, comprising:
- a bit cell coupled to a sensing circuit via a data path, wherein the bit cell includes a resistor configurable to a low resistive state and a high resistive state;
- a p-type metal-oxide semiconductor (PMOS) transistor having a drain connected to the data path;
- and
- a NAND gate having an output coupled to a gate of the PMOS transistor, wherein a first input of the NAND gate is controlled by an output node of the sensing circuit.
A method for implementing a sense amplifier, comprising:
- selectively injecting a current pulse to a bit cell line based on a previous logic value maintained at an output node, the bit cell line coupled to a bit cell that is configurable to a high or low resistance state;
- applying a read current to the bit cell and a reference resistor;
- comparing a voltage drop across the bit cell (D1) to a voltage reference across the reference resistor (R1);
- and
- outputting a logic output at the output node based on a comparison of R1 and D1.
Dependencies are inferred from the claim text.