Non-volatile memory octo mode program and erase operation method with reduced test time
AssigneeSK keyfoundry Inc.
InventorsWeon-Hwa Jeong, Young Chul Seo, Chul Geun Lim, Yong Hwan Kim, Sung Bum Park, Kee Sik Ahn
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Abstract
An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.
Claims15
A non-volatile memory device, comprising:
- a memory cell array comprising M word lines and N bit lines;
- a control logic device, configured to receive an external signal, and output an octo signal, a program signal and an erase signal;
- an address decoder, configured to receive the octo signal, and output a word line selection signal and a bit line selection signal;
- a high voltage generator, configured to receive the program signal and the erase signal, and output a read voltage and a write voltage;
- a row decoder, configured to receive the word line selection signal, and select a word line of the memory cell array;
- a column decoder, configured to receive the bit line selection signal, and select a bit line of the memory cell array;
- a page buffer, configured to receive the read voltage and the write voltage, and save data to be programmed;
- and
- a data latch, configured to save read data obtained from a read operation;
- wherein the non-volatile memory device is configured to simultaneously select non-contiguous word lines that are located every eighth word line among the M word lines and correspond to octo rows in response to the octo signal being applied to the address decoder,
- wherein a write voltage is configured to be applied to memory cells connected to the word lines corresponding to the octo rows, and
- wherein a voltage that is different from the write voltage is configured to be applied to memory cells connected to word lines, except for the word lines corresponding to the octo-rows.
A non-volatile memory device test time reduction method, the method comprising:
- transmitting an octo signal from a control logic device to an address decoder;
- transmitting the octo signal from the address decoder to a row decoder;
- transmitting the octo signal from the row decoder to a memory cell array;
- simultaneously selecting non-contiguous word lines that are located every eighth word line among the M word lines of the memory cell array and correspond to octo rows in response to the octo signal being applied to the address decoder;
- and
- performing a write operation simultaneously in memory cells connected to the word lines corresponding to the octo rows.
A non-volatile memory device, comprising:
- a memory cell array comprising M word lines and N bit lines;
- a control logic device, configured to output an octo signal, a program signal, and an erase signal;
- an address decoder, configured to receive the octo signal, and output a word line selection signal and a bit line selection signal;
- and
- a high voltage generator, configured to receive the program signal and the erase signal, and output a read voltage and a write voltage;
- wherein the non-volatile memory device is configured to select non-contiguous word lines that are located every eighth word line among the M word lines of the memory cell array and correspond to octo rows in response to the octo signal being applied to the address decoder.
Dependencies are inferred from the claim text.