Back to results
US 12,243,588 B2Granted
Semiconductor memory
AssigneeSK hynix Inc.
InventorJeong Hwan Song
Life of this patent
Estimating the term…
Abstract
A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.
Claims15
A semiconductor memory comprising:
- a first variable resistance element including a first terminal and a second terminal;
- a second variable resistance element including a first terminal, a second terminal, and a third terminal;
- a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element;
- a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element;
- a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element;
- and
- a second conductive line is electrically connected to the connection layer,
- wherein a read current flows through the first and second terminals of the first variable resistance element to read out data from the first variable resistance element, and a program current flows through the second and third terminals of the second variable resistance element to write data to the second variable resistance element, wherein a magnitude of the read current is greater than a magnitude of the program current,
- wherein a read operation of the second variable resistance element is performed to read out data from the second variable resistance element before reading out data from the first variable resistance element, and
- wherein a reprogram operation of the second variable resistance element to write data to the second variable resistance element is performed after reading out data from the first variable resistance element.
7 more elements
A semiconductor memory comprising:
- a first variable resistance element including a first terminal and a second terminal;
- a second variable resistance element including a first terminal, a second terminal, and a third terminal;
- a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element;
- a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element;
- a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element;
- and
- a second conductive line is electrically connected to the connection layer, wherein a first program current flows through the first and second terminals of the first variable resistance element to write data to the first variable resistance element, and a second program current flows through the second and third terminals of the second variable resistance element to write data to the second variable resistance element, wherein a magnitude of the first program current is smaller than a magnitude of the second program current,
- wherein a read operation of the first variable resistance element is performed to read out data from the first variable resistance element before writing data to the second variable resistance element, and
- wherein a reprogram operation of the first variable resistance element is performed to write data to the first variable resistance element after writing data to the second variable resistance element.
6 more elements
A semiconductor memory comprising:
- a first transistor including a first gate electrode that is disposed over a substrate;
- a second transistor including a second gate electrode that is disposed over the substrate;
- a first variable resistance element disposed over the substrate and electrically connected to a first terminal of the first transistor;
- a second variable resistance element disposed over the substrate and electrically connected to a first terminal of the second transistor;
- a source line disposed over the substrate and electrically connected in common to a second terminal of the first transistor and a second terminal of the second transistor;
- a connection layer disposed over the first and second variable resistance elements and electrically connected to the first variable resistance element while being in contact with an entire upper surface of the second variable resistance element;
- a bit line disposed over the connection layer and electrically connected to the connection layer;
- a first contact plug structured to connect the source line to the second terminal of the first transistor and the second terminal of the second transistor;
- a second contact plug structured to connect the first variable resistance element to the first terminal of the first transistor;
- a third contact plug structured to connect the second variable resistance element to the first terminal of the second transistor;
- and
- a fifth contact plug structured to connect the bit line to the connection layer.
9 more elements
Dependencies are inferred from the claim text.