In-memory zero value detection
AssigneeNeuroBlade Ltd.
InventorsElad Sity, Eliad Hillel
Life of this patent
Estimating the term…
Abstract
In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
Claims15
A memory unit comprising:
- a memory array including a plurality of memory banks;
- at least one controller configured to control at least one aspect of read operations relative to the plurality of memory banks;
- at least one multi-bit zero value detection logic unit configured to detect a multi-bit zero value associated with data and prevent retrieval of the data, wherein the data is stored in a particular address of the plurality of memory banks;
- at least one read-disable element configured to interrupt a read command associated with the particular address when the at least one multi-bit zero value detection logic unit detects the multi-bit zero value associated with the particular address;
- and
- wherein the at least one controller is configured to return a multi-bit zero value indicator to one or more circuits in response to a multi-bit zero value detection by the at least one multi-bit zero value detection logic unit.
A method for detecting a zero value in a particular address of a plurality of memory banks of a memory unit, comprising:
- receiving, from a circuit outside the memory unit, a request to read data stored in the particular address of the plurality of memory banks of the memory unit;
- activating, by a controller, in response to the received request, a zero value detection logic unit to detect the zero value in the particular address and prevent retrieval of the data;
- transmitting, by the controller, in response to the zero value detection by the zero value detection logic unit, a zero value indicator to the circuit;
- and
- configuring, by the controller, a read-disable element to interrupt a read command associated with the particular address when the zero value detection logic unit detects the zero value associated with the particular address.
A non-transitory computer-readable medium storing a set of instructions that are executable by a controller of a memory unit to perform operations to cause the memory unit to detect a zero value in a particular address of a plurality of memory banks of a memory unit, the operations comprising:
- receiving, from a circuit outside the memory unit, a request to read data stored in the particular address of the plurality of memory banks of the memory unit;
- activating, by a controller, in response to the received request, a zero value detection logic unit to detect the zero value in the particular address by a controller and prevent retrieval of the data;
- transmitting, by the controller, in response to the zero value detection by the zero value detection logic unit, a zero value indicator to the circuit;
- and
- configuring, by the controller, a read-disable element to interrupt a read command associated with the particular address when the zero value detection logic unit detects the zero value associated with the particular address.
Dependencies are inferred from the claim text.