Memory cell array unit
AssigneeSony Semiconductor Solutions Corporation
InventorsLui Sakai, Yasuo Kanda
Life of this patent
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Abstract
A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.
Claims7
A memory cell array unit comprising:
- a memory cell array that includes a plurality of n-bit allocation memory cells, wherein
- the memory cell array is configured to receive a control signal from a memory controller,
- the control signal comprises n-bit data, and
- the memory controller allocates the plurality of n-bit allocation memory cells to the n-bit data;
- and
- a microcontroller configured to:
- read and write the n-bit data from and into the memory cell array based on the control signal;
- receive n-bit write data and control data from a host computer;
- write n−1-bit write data into a plurality of n−1-bit allocation memory cells, wherein the n-bit write data includes n−1-bit write data;
- determine a defect in the plurality of n-bit allocation memory cells based on the n-bit write data and the control data;
- determine a defective allocation memory cell of the plurality of n-bit allocation memory cells based on the determined defect;
- and
- exclude the defective allocation memory cell and first data, wherein
- the n−1-bit write data includes the first data, and
- the first data corresponds to a least significant bit of the n−1-bit write data.
Dependencies are inferred from the claim text.