Integrated circuit margin measurement for structural testing
AssigneeProteantecs Ltd.
InventorsEvelyn Landman, Eyal Fayneh, Shai Cohen, Alex Khazin
Life of this patent
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Abstract
Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.
Claims20
A method for testing a semiconductor integrated circuit (IC), the method comprising:
- scanning test patterns into internal circuits of the semiconductor IC, the internal circuits of the semiconductor IC comprising a margin measurement sensor;
- measuring a margin, using the margin measurement sensor, the margin being measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time,
- wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time;
- and
- scanning out an output of the margin measurement sensor.
A tester device configured to test a semiconductor integrated circuit (IC) by:
- scanning test patterns from the tester device into a margin measurement sensor forming part of internal circuits of the semiconductor IC;
- and
- scanning out an output of the margin measurement sensor from the semiconductor IC to the tester device, to receive at the tester device one or more margin measurements performed by the margin measurement sensor, each margin being measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path of the semiconductor IC, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time, wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time.
A semiconductor integrated circuit (IC), comprising:
- structural test circuitry configured to receive test patterns and to run one or more structural tests on functional circuitry of the semiconductor IC;
- and
- a margin measurement sensor configured to measure a margin, the margin comprising a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by an adjustable delay time, wherein the adjustable delay time is introduced by having each of the test patterns cause an incremental adjustment of the delay time.
Dependencies are inferred from the claim text.