Asymmetric semiconductor memory device having electrically floating body transistor

A semiconductor memory array comprising:

• a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell selected from at least first and second states;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a first insulating region located above said floating body region;
• second insulating regions adjacent to said floating body region;
• third and fourth regions located below said second insulating regions;
• a buried layer region located below said floating body region, said second insulating regions and said third and fourth regions, and spaced from said second insulating regions,
• wherein said third and fourth regions are electrically connected to said buried layer region;
• wherein said floating body region is bounded by said first insulating region, said second insulating regions, said third and fourth regions, and said buried layer region;
• and
• wherein said buried layer region is commonly connected to at least two of said semiconductor memory cells.

An integrated circuit comprising:

• a semiconductor memory array comprising:
• a plurality of semiconductor memory cells arranged in a matrix of rows and columns,
• wherein each said semiconductor memory cell includes:
• a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell selected from at least first and second states;
• a first region in electrical contact with said floating body region;
• a second region in electrical contact with said floating body region and spaced apart from said first region;
• a gate positioned between said first and second regions;
• a first insulating region located above said floating body region;
• second insulating regions adjacent to said floating body region;
• third and fourth regions located below said second insulating regions;
• a buried layer region located below said floating body region, said second insulating regions and said third and fourth regions, and spaced from said second insulating regions,
• wherein said third and fourth regions are electrically connected to said buried layer region;
• wherein said floating body region is bounded by said first insulating region, said second insulating regions, said third and fourth regions, and said buried layer region;
• wherein said buried layer region is commonly connected to at least two of said semiconductor memory cells;
• and
• a control circuit configured to perform a holding operation on said array.