Heterostructure oxide semiconductor vertical gate-all-around (VGAA) transistor and methods for making the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGerben Doornbos, Blandine Duriez, Marcus Johannes Henricus Van Dal
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Abstract
A method of forming a semiconductor device includes forming a contact metal layer, forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order, and forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.
Claims20
A method of forming a semiconductor transistor, comprising:
- forming a contact metal layer over a first interlayer dielectric (ILD) layer;
- depositing and removing oxide semiconductor layers to form a selected vertical structure as a channel structure over the contact metal layer, wherein the channel structure extends up from the contact metal layer in a first direction and the channel structure comprises:
- a channel region;
- and
- two source/drain regions located on respective sides of the channel region, wherein the channel region and the two source/drain regions are stacked up along the first direction;
- depositing a spacer oxide layer, dielectric layer, and gate material sequentially over the channel structure;
- removing gate material to form a selected gate structure, wherein the gate structure is configured to surround the channel region;
- depositing a second ILD layer and opening vias in the second ILD layer to the gate structure, channel structure, and contact metal layer;
- and
- filling the vias with metal to form contact structures.
A method of forming a semiconductor device, comprising:
- forming a contact metal layer;
- forming a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order;
- and
- forming a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure.
A method of forming a semiconductor device, comprising:
- forming a transistor, comprising:
- a contact metal layer;
- a channel structure on the contact metal layer, wherein the channel structure comprises a first source/drain region, a channel region and a second source/drain region stacked in that order;
- and
- a gate structure around the channel region, such that an upper surface of the gate structure is substantially coplanar with an upper surface of the channel structure;
- and
- forming a memory element on the transistor and connected to the transistor in series.
Dependencies are inferred from the claim text.