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US 12,237,953 B2Granted
Multi-level signaling in memory with wide system interface
AssigneeMicron Technology, Inc.
InventorsTimothy M. Hollis, Markus Balb, Ralf Ebert
Life of this patent
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Abstract
Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
Claims20
An apparatus, comprising:
- an array of memory cells;
- a controller configured to control operation of memory cells in the array of memory cells;
- a signaling interface coupled with the array of memory cells and configured to generate a signal modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells;
- and
- a receiver configured to determine the logic state represented by the signal modulated using the first modulation scheme communicated across at least one channel of a plurality of channels between the array of memory cells and the controller.
2 more elements
A method, comprising:
- identifying, by a controller of a memory device, information to be written to an array of memory cells;
- generating, by the controller, a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells;
- and
- transmitting, by the controller, the signal to the array of memory cells across at least one channel of a plurality of channels located between the controller and the array of memory cells.
1 more element
An apparatus, comprising:
- an array of memory cells;
- and
- a controller coupled with the array of memory cells and configured to cause the apparatus to:
- identify information to be written to an array of memory cells;
- generate a signal that represents a plurality of bits of the identified information, wherein the signal is modulated using a first modulation scheme based at least in part on a logic state read from the array of memory cells;
- and
- transmit the signal to the array of memory cells across at least one channel of a plurality of channels located between the controller and the array of memory cells.
4 more elements
Dependencies are inferred from the claim text.