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US 12,237,838 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorTakayuki Ootani
Life of this patent
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Abstract
A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.
Claims9
A semiconductor device comprising:
- a main device which operates in a delayed lockstep mode;
- a sub device which operates in parallel to the main device in the delayed lockstep mode;
- a first delay circuit which delays an output of the main device;
- and
- a first switching circuit which switches the main device to the sub device according to first failure information of the main device,
- wherein the main device includes a first master central processing unit, a first checker central processing unit, and a first comparator which compares an output of the first master central processing unit with an output of the first checker central processing unit to output the first failure information, and
- wherein the sub device includes a second master central processing unit, a second checker central processing unit, and a second comparator which compares an output of the second master central processing unit with an output of the second checker central processing unit to output second failure information.
4 more elements
Dependencies are inferred from the claim text.