Vertical tunnel field-effect transistor with u-shaped gate and band aligner

A method of forming a tunnel field-effect transistor, comprising:

• forming a first source or drain layer over a substrate;
• forming a first channel layer over the first source or drain layer, the first channel layer including a first portion and a second portion arranged laterally with respect to the first portion;
• forming a second channel layer over the first portion of the first channel layer, the second channel layer including a same conductivity type as the first channel layer;
• forming a second source or drain layer over the second channel layer;
• forming a first gate structure over the second portion of the first channel layer, adjacent to the first channel layer only from a vertical direction and adjacent to a first sidewall of the second channel layer from a lateral direction that is traverse to the vertical direction;
• and
• forming a second gate structure over the first source or drain layer, the second gate structure in contact with a second sidewall of the second channel layer from the lateral direction and in direct contact with the first source or drain layer only from a vertical direction,
• wherein each of the second source or drain layer, the first channel layer and the second channel layer includes a same doping type that is different from a doping type of the first source or drain layer.

A method, comprising:

• forming a first semiconductor layer of a first III-V compound semiconductor material over a substrate, the first semiconductor layer including dopants of a first conductivity type;
• forming a second semiconductor layer of a second III-V compound semiconductor material over the first semiconductor layer, the second semiconductor layer including dopants of a second conductivity type that is different from the first conductivity type;
• forming a first gate structure positioned over and contacting a first upper portion of the second semiconductor layer only from a vertical direction;
• and
• forming two vertical semiconductor stacks respectively adjacent to two opposite sides of the gate structure from a lateral direction, each of the two vertical semiconductor stacks including a third semiconductor layer and a fourth semiconductor layer, the third semiconductor layer having a same second III-V compound semiconductor material as the second semiconductor layer but with a different material composition, each of the third semiconductor layer and the fourth semiconductor layer including dopants of the second conductivity type, the third semiconductor layer in contact with the first gate structure from a lateral direction;
• and
• forming a second gate structure over the first semiconductor layer, the second gate structure in contact with at least one of the two vertical semiconductor stacks from the lateral direction and in direct contact with the first semiconductor layer only from the vertical direction.