# US 12,237,305 B2 · Integrated circuit package having wirebonded multi-die stack

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- Number: US 12,237,305 B2
- Document ID: US12237305B2
- Status: Granted
- Kind: B2
- Application number: 17/958,298
- Filed: 2022-09-30
- Published: 2023-01-26
- Granted: 2025-02-25
- Earliest claimed: 2018-03-08
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Thorsten Meyer; Pauli Jaervinen; Richard Patten
- Web page: https://patentgrep.com/patent/US12237305B2

## CPC

- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/43: Layouts of interconnections
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/50: Bond wires
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

## Claims

### Claim 1

A semiconductor package, comprising:
a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
a redistribution layer, the redistribution layer coupled to the active side of the first die, and the redistribution layer coupled to a plurality of package level interconnects;
a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first die;
a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first die;
a first encapsulation layer laterally surrounding and in contact with the first die;
an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first die, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die;
a third die above the second die, the third die having an active side and a backside opposite the active side, the active side of the third die having a plurality of die level interconnects thereon, the backside of the third die facing the active side of the second die;
a first wire bond coupling one of the plurality of die level interconnects of the second die to the first via bar;
a second wire bond coupling one of the plurality of die level interconnects of the third die to the second via bar; and
a second encapsulation layer laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third die.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, further comprising:
a spacer between the backside of the third die and the active side of the second die.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the second encapsulation layer is laterally adjacent the spacer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, further comprising:
a first conductive pad between the first wire bond and the first via bar; and
a second conductive pad between the second wire bond and the second via bar.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of package level interconnects comprises a plurality of solder balls below the first die and outside of a periphery of the first die.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of package level interconnects comprises a plurality of solder balls below the first die and within a periphery of the first die.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein the plurality of package level interconnects comprises a first plurality of solder balls below the first die and within a periphery of the first die, and a second plurality of solder balls below the first die and outside of the periphery of the first die.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, further comprising:
a second redistribution layer between the redistribution layer and the plurality of package level interconnects.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein the second die and the third die are vertically aligned with one another.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein the first encapsulation layer has an uppermost surface above the backside of the first die.

### Claim 11 (depends on 1)

The semiconductor package of claim 1, further comprising:
a fourth die having an active side coupled to a die side of the redistribution layer.

### Claim 12

An integrated circuit (IC) assembly comprising:
a semiconductor package, comprising:
a first integrated circuit having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
a redistribution layer, the redistribution layer coupled to the active side of the first integrated circuit, and the redistribution layer coupled to a plurality of package level interconnects;
a first via bar laterally adjacent to and distanced apart from a first edge of the first integrated circuit, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first integrated circuit;
a second via bar laterally adjacent to and distanced apart from a second edge of the first integrated circuit opposite the first edge of the first integrated circuit, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first integrated circuit;
a first encapsulation layer laterally surrounding and in contact with the first integrated circuit;
an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first integrated circuit, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
a second integrated circuit above the first integrated circuit, the second integrated circuit having an active side and a backside opposite the active side, the active side of the second integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the second integrated circuit facing the backside of the first integrated circuit;
a third integrated circuit above the second integrated circuit, the third integrated circuit having an active side and a backside opposite the active side, the active side of the third integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the third integrated circuit facing the active side of the second integrated circuit;
a first wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the second integrated circuit to the first via bar;
a second wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the third integrated circuit to the second via bar; and
a second encapsulation layer laterally adjacent the second integrated circuit, the third integrated circuit, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third integrated circuit; and
a circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects.

### Claim 13 (depends on 12)

The IC assembly of claim 12, wherein the semiconductor package includes a processor.

### Claim 14 (depends on 12)

The IC assembly of claim 12, wherein the semiconductor package includes a memory.

### Claim 15 (depends on 12)

The IC assembly of claim 12, further comprising one or more components coupled to the circuit board, the one or more components selected from the group consisting of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera.

### Claim 16 (depends on 12)

The IC assembly of claim 12, wherein the semiconductor package further comprises a spacer between the backside of the third integrated circuit and the active side of the second integrated circuit.

### Claim 17 (depends on 16)

The IC assembly of claim 16, wherein the second encapsulation layer is laterally adjacent the spacer.

### Claim 18 (depends on 12)

The IC assembly of claim 12, wherein the semiconductor package further comprises a first conductive pad between the first wire bond and the first via bar, and a second conductive pad between the second wire bond and the second via bar.

### Claim 19 (depends on 12)

The IC assembly of claim 12, wherein the plurality of package level interconnects of the semiconductor package comprises a first plurality of solder balls below the first integrated circuit and within a periphery of the first integrated circuit, and a second plurality of solder balls below the first integrated circuit and outside of the periphery of the first integrated circuit.

### Claim 20 (depends on 12)

The IC assembly of claim 12, wherein the semiconductor package further comprises a second redistribution layer between the redistribution layer and the plurality of package level interconnects.