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US 12,237,049 B2Granted
Semiconductor memory devices having efficient serializers therein for transferring data
AssigneeSamsung Electronics Co., Ltd.
InventorsSanguk Lee, Daehyun Kwon, Jang-Woo Ryu, Hangi Jung
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Abstract
An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.
Claims19
An integrated circuit memory device, comprising:
- a memory core;
- control logic configured to control the memory core to:
- (i) output parallel data, and (ii) generate multiple internal clock signals in response to a clock signal received from a host;
- and
- a data transmitting unit including a serializer configured to convert the parallel data into serial data, said serializer comprising:
- a plurality of multiplexers that are each configured to output a respective inverted data signal based on one of the parallel data and two of the internal clock signals having different phases relative to each other;
- and
- a serializing circuit configured to output the serial data by logically combining the inverted data signals output from the plurality of multiplexers;
- and
- wherein each of the plurality of multiplexers acquires inverted data of the one of the parallel data between rising edges of the corresponding two internal clock signals and generates therefrom a corresponding one of the inverted data signals.
7 more elements
An integrated circuit memory device, comprising:
- a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data, using a Boolean logic circuit configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof;
- wherein the serializer comprises:
- a first multiplexer, which is configured to receive a first of the plurality of bits of parallel read data and first and second ones of the plurality of clock signals;
- and
- a second multiplexer, which is configured to receive a third of the plurality of bits of parallel read data and third and fourth ones of the plurality of clock signals.
2 more elements
A serializer to convert first data, second data, third data, and fourth data, which are input in parallel, to serial data, the serializer comprising:
- a first multiplexer configured to output a first inverted data signal corresponding to the first data, based on a first clock signal and a second clock signal;
- a second multiplexer configured to output a second inverted data signal corresponding to the third data, based on a third clock signal and a fourth clock signal;
- a third multiplexer configured to output a third inverted data signal corresponding to the second data, based on the second clock signal and the third clock signal;
- a fourth multiplexer configured to output a fourth inverted data signal corresponding to the fourth data, based on the fourth clock signal and the first clock signal;
- and
- a serializing circuit configured to output the serial data by logically combining the first inverted data signal, the second inverted data signal, the third inverted data signal, and the fourth inverted data signal,
- wherein the serializing circuit includes:
- a first NAND circuit configured to output a first intermediate signal having the first data and the third data alternately aligned at a specific time interval, by performing a NAND operation for the first inverted data signal and the second inverted data signal;
- a second NAND circuit configured to output a second intermediate signal having the second data and the fourth data alternately aligned at a specific time interval, by performing a NAND operation for the third inverted data signal and the fourth inverted data signal;
- a third NAND circuit configured to output a first inverted intermediate signal by performing a NAND operation for the first intermediate signal and a power supply voltage signal;
- a fourth NAND circuit configured to output a second inverted intermediate signal by performing a NAND operation for the second intermediate signal and the power supply voltage signal;
- and
- a fifth NAND circuit configured to output the serial data having the first data, the second data, the third data, and the fourth data sequentially aligned, by performing a NAND operation for the first inverted intermediate signal and the second inverted intermediate signal.
10 more elements
Dependencies are inferred from the claim text.